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1. 发明授权

US06539064B1 Multiple data rate filtered modulation system for digital data 有权
标题翻译：用于数字数据的多数据速率滤波调制系统
公开(公告)号：US06539064B1
公开(公告)日：2003-03-25
申请号：US09234948
申请日：1999-01-21
申请人： Michael K. Ellis , Thomas J. Schuster , Ronald L. Mahany , Daniel E. Alt
发明人： Michael K. Ellis , Thomas J. Schuster , Ronald L. Mahany , Daniel E. Alt
IPC分类号： H04L2732
CPC分类号： H04L27/2017
摘要： A multi-rate data modulation circuit includes a multi-rate data conversion circuit and a modulator such as a direct digital synthesis circuit. The multi-rate data conversion circuit receives digital data at varying data rates, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. The direct digital synthesis circuit receives the converted output and synthesizes a modulated output signal based upon the converted output. The multi-rate data conversion circuit may include a multi-rate converter, a multi-rate digital data filter, an output scaler and an adder. The multi-rate converter receives the digital data, the data rate input and a clock signal and converts the digital data to converted digital data. The multi-rate digital data filter receives the converted digital data and produces a filtered digital output. The output scaler receives the filtered digital output and produces a scaled and filtered digital output. Finally, the adder combines the scaled and filtered digital output with a center frequency input and produces the converted output. The multi-rate digital data filter may include a look-up table that produces filter parameters based upon the converted digital data and that operates at multiple data rates. The multi-rate digital data filter may include a digital data filter look-up table, a data rate decode circuit and a plurality of multiplexors. In such case, the data rate decode circuit receives the data rate input and produces control signals therefrom. Each of the plurality of multiplexors receives a portion of the converted digital data and control signals from the data rate decode circuit such that the multiplexors selectively provide the converted digital data to the digital data filter look-up table to produce the filtered digital output.
摘要翻译：多速率数据调制电路包括多速率数据转换电路和诸如直接数字合成电路的调制器。多速率数据转换电路以变化的数据速率接收数字数据，接收对应于数字数据的数据速率输入，并且基于数据速率输入将数字数据转换成转换的输出。直接数字合成电路接收转换后的输出，并根据转换后的输出合成调制输出信号。多速率数据转换电路可以包括多速率转换器，多速率数字数据滤波器，输出缩放器和加法器。多速率转换器接收数字数据，数据速率输入和时钟信号，并将数字数据转换为转换的数字数据。多速率数字数据滤波器接收转换的数字数据并产生滤波后的数字输出。输出缩放器接收滤波后的数字输出，并产生一个缩放和滤波的数字输出。最后，加法器将缩放和滤波的数字输出与中心频率输入相结合，并产生转换的输出。多速率数字数据滤波器可以包括基于转换的数字数据产生滤波器参数并以多个数据速率操作的查找表。多速率数字数据滤波器可以包括数字数据滤波器查找表，数据速率解码电路和多个多路复用器。在这种情况下，数据速率解码电路接收数据速率输入并产生控制信号。多个多路复用器中的每一个从数据速率解码电路接收转换的数字数据和控制信号的一部分，使得多路复用器选择性地将转换后的数字数据提供给数字数据滤波器查找表，以产生经滤波的数字输出。

2. 发明授权

US07298791B1 Multiple date rate filtered modulation system for digital data 有权
标题翻译：用于数字数据的多日期滤波调制系统
公开(公告)号：US07298791B1
公开(公告)日：2007-11-20
申请号：US10397057
申请日：2003-03-25
申请人： Ronald L. Mahany , Thomas J. Schuster , Michael K. Ellis , Daniel E. Alt
发明人： Ronald L. Mahany , Thomas J. Schuster , Michael K. Ellis , Daniel E. Alt
IPC分类号： H04L25/49
CPC分类号： H04L27/2017
摘要： In an exemplary embodiment, a multi-rate data conversion circuit receives digital data at varying data rates, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. A direct digital synthesis circuit receives the converted output and synthesizes a modulated output signal based upon the converted output. A multi-rate converter receives the digital data, the data rate input and a clock signal and converts the digital data to converted digital data. A multi-rate digital data filter receives the converted digital data and produces a filtered digital output. An output scaler receives the filtered digital output and produces a scaled and filtered digital output. Finally, an adder combines the scaled and filtered digital output with a center frequency input and produces the converted output.
摘要翻译：在一个示例性实施例中，多速率数据转换电路以变化的数据速率接收数字数据，接收对应于数字数据的数据速率输入，并且基于数据速率输入将数字数据转换成转换的输出。直接数字合成电路接收转换的输出，并根据转换的输出合成调制的输出信号。多速率转换器接收数字数据，数据速率输入和时钟信号，并将数字数据转换为转换的数字数据。多速率数字数据滤波器接收转换的数字数据并产生滤波数字输出。输出缩放器接收滤波后的数字输出并产生缩放和滤波的数字输出。最后，加法器将缩放和滤波的数字输出与中心频率输入相结合，并产生转换的输出。

3. 发明授权

US5990733A Delay line ramp demodulator 失效
标题翻译：延迟线斜坡解调器
公开(公告)号：US5990733A
公开(公告)日：1999-11-23
申请号：US26062
申请日：1998-02-19
申请人： Ronald L. Mahany , Thomas J. Schuster
发明人： Ronald L. Mahany , Thomas J. Schuster
IPC分类号： H03D3/02
CPC分类号： H03D3/04
摘要： An integrated circuit includes a demodulator having delay circuitry and demodulation control circuitry that may be fully formed within a common integrated circuit. The delay circuitry receives an input signal and generates a delayed input signal. The demodulation control circuitry generates a demodulated output based upon the input signal and the delayed input signal that has a level that is proportional to, or a finction of, a period of a respective cycle of the input signal. The demodulation control circuitry includes pulse generation circuitry, pulse delay circuitry, pulse conversion circuitry and sampling circuitry. The pulse generation circuitry generates a signal pulse based upon the input signal and the delayed input signal with a duration that is proportional to at least one period of the input signal. The pulse delay circuitry generates a delayed signal pulse based upon the signal pulse. The pulse conversion circuitry generates a converted signal that has a level based upon the duration of the signal pulse. The sampling circuitry samples the converted signal based upon a sample pulse to generate the demodulated output based upon the level of the converted signal. The delay circuitry and pulse delay circuitry each include a plurality of cascaded semiconductive elements that, in combination, produce a desired delay duration.
摘要翻译：集成电路包括具有延迟电路和解调控制电路的解调器，其可以完全形成在公共集成电路内。延迟电路接收输入信号并产生延迟的输入信号。解调控制电路基于输入信号和延迟的输入信号产生解调输出，该输入信号具有与输入信号的相应周期的周期成比例的水平或功能。解调控制电路包括脉冲产生电路，脉冲延迟电路，脉冲转换电路和采样电路。脉冲产生电路基于输入信号和延迟的输入信号产生具有与输入信号的至少一个周期成比例的持续时间的信号脉冲。脉冲延迟电路基于信号脉冲产生延迟的信号脉冲。脉冲转换电路产生具有基于信号脉冲持续时间的电平的转换信号。采样电路基于采样脉冲对转换的信号进行采样，以基于转换信号的电平产生解调输出。延迟电路和脉冲延迟电路各自包括多个级联的半导体元件，其组合地产生期望的延迟持续时间。

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