专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08067966B2 Voltage controlled delay loop and method with injection point control 有权
标题翻译：电压控制延时回路和注入点控制方法
公开(公告)号：US08067966B2
公开(公告)日：2011-11-29
申请号：US10999900
申请日：2004-11-30
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/0814 , H03L7/087 , H04L7/0337
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises a plurality of delay elements; and an input that selectively injects a reference clock into any one of the plurality of delay elements. The plurality of delay elements are connected in series, such as in a loop. In one exemplary implementation, each delay element has an associated multiplexer that selects one of the reference clock and a signal from a previous delay element.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟环包括多个延迟元件; 以及输入，其选择性地将参考时钟注入到所述多个延迟元件中的任一个中。多个延迟元件串联连接，例如循环。在一个示例性实现中，每个延迟元件具有相关联的多路复用器，其选择参考时钟之一和来自先前延迟元件的信号。

2. 发明授权

US07848473B2 Phase interpolator having a phase jump 有权
标题翻译：相位内插器具有相位跳变
公开(公告)号：US07848473B2
公开(公告)日：2010-12-07
申请号：US11020021
申请日：2004-12-22
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H04L7/04
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/091 , H04L7/0025 , H04L7/0337
摘要： A method and apparatus are disclosed for generating phase controlled data, based on a roaming tap interpolator. The present invention recognizes that roaming tap interpolators have inherent nonlinearities and discontinuities at the boundaries of each interpolation region. A roaming tap interpolator is disclosed that shifts the interpolation curve in time in order to avoid the undesired artifacts in the interpolation curve. A roaming tap interpolator generally comprises a plurality of delay elements that delays a first signal to generate a plurality of interpolation regions each having an associated phase; a multiplexer to select one or more of the interpolation regions; and an interpolator to process the selected one or more of the interpolation regions to generate a second signal. In addition, according to the present invention, the roaming tap interpolator includes a delay unit that selectively delays one or more of the first signal and the second signal to generate an interpolation signal, the interpolation signal selectively having a first phase or a second phase.
摘要翻译：公开了一种基于漫游抽头内插器来产生相位控制数据的方法和装置。本发明认识到，漫游抽头内插器在每个内插区域的边界处具有固有的非线性和不连续性。公开了一种漫游抽头内插器，其在时间上偏移插值曲线，以避免插值曲线中的不需要的伪影。漫游抽头内插器通常包括多个延迟元件，其延迟第一信号以产生每个具有相关联的相位的多个内插区域; 多路复用器，用于选择一个或多个插值区域; 以及内插器，用于处理所选择的一个或多个内插区域以产生第二信号。此外，根据本发明，漫游抽头内插器包括延迟单元，其选择性地延迟第一信号和第二信号中的一个或多个以产生内插信号，该内插信号选择性地具有第一相位或第二相位。

3. 发明授权

US07190198B2 Voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟回路
公开(公告)号：US07190198B2
公开(公告)日：2007-03-13
申请号：US10999889
申请日：2004-11-30
申请人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
发明人： Ronald L. Freyman , Vladimir Sindalovsky , Lane A. Smith , Craig B. Ziemer
IPC分类号： H03L7/06
CPC分类号： G06F1/04
摘要： A voltage controlled delay loop and method are disclosed for clock and data recovery applications. The voltage controlled delay loop generates clock signals having similar frequency and different phases. The voltage controlled delay loop comprises at least one delay element to generate at least two phases of a reference clock; a central interpolator for interpolating the at least two phases of the reference clock to generate an interpolated signal; and an input that injects the interpolated signal into a delay stage. The central interpolator provides a fine phase control. In addition, a coarse phase control can optionally be achieved by selectively injecting the interpolated signal into a given delay stage. A further voltage controlled delay loop is disclosed with coarse and fine phase control using a number of interpolators.
摘要翻译：公开了用于时钟和数据恢复应用的电压控制延迟环路和方法。电压控制延迟环路产生具有相似频率和不同相位的时钟信号。电压控制延迟回路包括至少一个延迟元件以产生参考时钟的至少两个相位; 中央内插器，用于内插参考时钟的至少两个相位以产生内插信号; 以及将内插信号注入延迟级的输入。中央插值器提供精细的相位控制。此外，可以通过选择性地将内插信号注入到给定的延迟级中来可选地实现粗略的相位控制。公开了使用多个内插器的粗略和精细相位控制的另一个电压控制延迟回路。

4. 发明授权

US07173459B2 Trimming method and apparatus for voltage controlled delay loop with central interpolator 有权
标题翻译：具有中央插补器的电压控制延迟环微调方法和装置
公开(公告)号：US07173459B2
公开(公告)日：2007-02-06
申请号：US11020022
申请日：2004-12-22
申请人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0818
摘要： Methods and apparatus are provided for trimming a desired delay element in a voltage controlled delay loop. The disclosed trimming process comprises the steps of obtaining a first phase signal of a reference clock; applying the first phase signal along a first path to the desired delay element and a common delay element connected in series to the desired delay element; applying the reference clock along a second path to a first delay element and the common delay element; measuring a delay difference between the first and second paths at an output of the common delay element; and adjusting a delay of the desired delay element based on the measured delay difference. The trimming method may be repeated for each delay element in a voltage controlled delay loop.
摘要翻译：提供了用于在电压控制的延迟环中修整期望的延迟元件的方法和装置。所公开的修剪过程包括获得参考时钟的第一相位信号的步骤; 将第一相位信号沿着第一路径施加到期望的延迟元件和与期望的延迟元件串联连接的公共延迟元件; 沿着第二路径将参考时钟施加到第一延迟元件和公共延迟元件; 测量所述公共延迟元件的输出处的所述第一和第二路径之间的延迟差; 以及基于所测量的延迟差来调整所述延迟元件的延迟。可以在电压控制的延迟环路中对每个延迟元件重复修整方法。

5. 发明授权

US07495494B2 Parallel trimming method and apparatus for a voltage controlled delay loop 有权
标题翻译：用于电压控制延迟回路的平行修整方法和装置
公开(公告)号：US07495494B2
公开(公告)日：2009-02-24
申请号：US11141703
申请日：2005-05-31
申请人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
发明人： Ronald L. Freyman , Mohammad S. Mobin , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H04L7/0337
摘要： A parallel trimming method and apparatus are provided for a voltage controlled delay loop. A plurality of delay units in a voltage controlled delay loop are trimmed. Each delay unit comprises a delay element and a latch buffer. A reference signal is applied to each of the delay units and a position of an edge (such as a rising or falling edge) associated with each of the delay units is identified. The edges of the delay units are then aligned by adjusting a trim setting of the respective latch buffer.
摘要翻译：提供了一种用于电压控制延迟环路的并行修整方法和装置。电压控制延迟环中的多个延迟单元被修整。每个延迟单元包括延迟元件和锁存缓冲器。参考信号被施加到每个延迟单元，并且识别与每个延迟单元相关联的边缘（例如上升沿或下降沿）的位置。然后通过调整相应的锁存缓冲器的修整设置来对准延迟单元的边缘。

6. 发明授权

US08165253B2 Methods and apparatus for serializer/deserializer transmitter synchronization 有权
标题翻译：串行器/解串器发射机同步的方法和装置
公开(公告)号：US08165253B2
公开(公告)日：2012-04-24
申请号：US12200106
申请日：2008-08-28
申请人： Christopher J. Abel , Vladimir Sindalovsky , Lane A. Smith
发明人： Christopher J. Abel , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H04L7/00
CPC分类号： H04J3/0685
摘要： Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.
摘要翻译：提供串行器/解串器发射机同步的方法和装置。通过在一个或多个信道中产生同步请求，在一个或多个串行器/解串器设备中同步多个信道; 响应于所述同步请求产生使能信号; 以及响应于使能信号，仅产生一个同步信号的一个或多个周期的门控同步信号。门控同步信号可以可选地在同步信号的一个或多个周期之后被断言。

7. 发明申请

US20100054386A1 METHODS AND APPARATUS FOR SERIALIZER/DESERIALIZER TRANSMITTER SYNCHRONIZATION 有权
标题翻译：串行/解复用器发射机同步的方法和装置
公开(公告)号：US20100054386A1
公开(公告)日：2010-03-04
申请号：US12200106
申请日：2008-08-28
申请人： Christopher J. Abel , Vladimir Sindalovsky , Lane A. Smith
发明人： Christopher J. Abel , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H04L7/00
CPC分类号： H04J3/0685
摘要： Methods and apparatus are provided for serializer/deserializer transmitter synchronization. A plurality of channels are synchronized in one or more serializer/deserializer devices by generating a synchronization request in one or more of the channels; generating an enable signal in response to the synchronization request; and generating a gated synchronization signal for only one or more periods of a synchronization signal in response to the enable signal. The gated synchronization signal can optionally be deasserted after the one or more periods of a synchronization signal.
摘要翻译：提供串行器/解串器发射机同步的方法和装置。通过在一个或多个信道中产生同步请求，在一个或多个串行器/解串器设备中同步多个信道; 响应于所述同步请求产生使能信号; 以及响应于使能信号，仅产生一个同步信号的一个或多个周期的门控同步信号。门控同步信号可以可选地在同步信号的一个或多个周期之后被断言。

8. 发明授权

US07599461B2 Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data in the presence of an adverse pattern 有权
标题翻译：用于在存在不利模式的情况下使用DFE检测数据产生用于判决反馈均衡器的一个或多个时钟信号的方法和装置
公开(公告)号：US07599461B2
公开(公告)日：2009-10-06
申请号：US11541498
申请日：2006-09-29
申请人： Pervez M. Aziz , Vladimir Sindalovsky , Lane A. Smith
发明人： Pervez M. Aziz , Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H03D3/24
CPC分类号： H04L25/03057 , H04L7/0062
摘要： Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data, in the presence of an adverse pattern, such as a Nyquist pattern. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. One or more of said phase updates are modified by the present invention if said DFE detected data satisfies one or more predefined conditions. A number of mechanisms are disclosed for qualifying or modifying the DFE phase detector updates based on the detected data pattern.
摘要翻译：提供的方法和装置用于在诸如奈奎斯特图案之类的不利图案的存在下，使用DFE检测数据产生用于判决反馈均衡器的一个或多个时钟信号。使用数据时钟和转换时钟对接收到的信号进行采样，以生成数据采样信号和转换采样信号。为每个数据采样和转换采样信号获得DFE校正，以产生DFE检测数据和DFE转换数据。 DFE检测数据和DFE转换数据然后被施加到产生信号以调整数据时钟和转换时钟中的一个或多个的相位的相位检测器。如果所述DFE检测到的数据满足一个或多个预定条件，则本发明修改所述相位更新中的一个或多个。公开了用于基于检测到的数据模式来限定或修改DFE相位检测器更新的多种机制。

9. 发明授权

US07526033B2 Serializer deserializer (SERDES) testing 有权
标题翻译：串行器解串器（SERDES）测试
公开(公告)号：US07526033B2
公开(公告)日：2009-04-28
申请号：US11051801
申请日：2005-02-04
申请人： Vladimir Sindalovsky , Lane A. Smith
发明人： Vladimir Sindalovsky , Lane A. Smith
IPC分类号： H04B3/00 , H04J3/04
CPC分类号： G01R31/31716
摘要： The various embodiments of the invention provide an apparatus, system and method of testing a serializer and deserializer data communication apparatus (SERDES). The serializer and deserializer data communication apparatus has a plurality of serialize data communication channels adapted to convert parallel data to serial data and a plurality of deserialize data communication channels adapted to convert serial data to parallel data. An exemplary method provides for coupling an output of a serialize data communication channel and an input of a deserialize data communication channel to provide a serial data loop-back connection and coupling an output of a deserialize data communication channel and an input of a serialize data communication channel to provide a parallel data loop-back connection. Input test data is provided to a first serialize or deserialize data communication channel, and is successively serialized and deserialized through each corresponding serialize data communication channel and deserialize data communication channel to provide output test data. The output test data and the input test data are then compared, with SERDES devices having acceptable or unacceptable bit error rates respectively designated as passed or failed.
摘要翻译：本发明的各种实施例提供了测试串行器和解串器数据通信设备（SERDES）的装置，系统和方法。串行器和解串器数据通信装置具有多个串行化数据通信通道，适用于将并行数据转换为串行数据，以及多个反序列化数据通信通道，适用于将串行数据转换为并行数据。一种示例性方法提供串行化数据通信信道的输出和反序列化数据通信信道的输入，以提供串行数据环回连接，并将反序列化数据通信信道的输出和序列化数据通信的输入通道提供并行数据环回连接。输入测试数据提供给第一个串行化或反序列化数据通信通道，并通过每个相应的串行化数据通信通道连续序列化和反序列化，并对数据通信通道进行反序列化，提供输出测试数据。然后将输出测试数据和输入测试数据与具有分别指定为通过或失败的可接受或不可接受的误码率的SERDES器件进行比较。

10. 发明申请

US20130009679A1 BANG-BANG PHASE DETECTOR WITH HYSTERESIS 审中-公开
标题翻译： BANG-BANG相位检测器与HYSTERESIS
公开(公告)号：US20130009679A1
公开(公告)日：2013-01-10
申请号：US13178812
申请日：2011-07-08
申请人： Vladimir Sindalovsky , Lane A. Smith , Jung Cho
发明人： Vladimir Sindalovsky , Lane A. Smith , Jung Cho
IPC分类号： H03L7/06
CPC分类号： H03L7/00 , H03L7/06 , H03L7/08
摘要： In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state.
摘要翻译：在所描述的实施例中，具有数字爆炸相位检测器（BBPD）的时钟对准系统采用数字实现的滞后。第一个BBPD被用于相位控制环路，该相位控制环路比较来自两个不同时钟域源的相位，其中一个时钟源源作为相位控制环路的参考时钟。采用具有延迟参考时钟的第二个BBPD来解决第一个BBPD所看到的模糊相位关系。检查被定义为第一BBPD和第二BBPD的当前值的矢量的BBPD矢量的初始状态。基于BBPD矢量的初始状态和后续状态，允许非参考时钟通过相位控制回路的动作自然地移动到锁定状态，或者被迫使其相位顺时针或逆时针旋转以达到锁定状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式