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1. 发明授权

US5983298A Industrial controller permitting removal and insertion of circuit cards while under power 失效
标题翻译：工业控制器允许在电源下取出和插入电路卡
公开(公告)号：US5983298A
公开(公告)日：1999-11-09
申请号：US561506
申请日：1995-11-20
申请人： Ronald E. Schultz , William E. Floro , Otomar Schmidt
发明人： Ronald E. Schultz , William E. Floro , Otomar Schmidt
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4081 , Y02B60/1228 , Y02B60/1235
摘要： A circuit card of an industrial controller may be removed or inserted under power without loss of memory or disturbance to the power supplies of other modules through the use of a power failure signal derived from shortened pins on the connector between the card and the industrial controller. The power failure signal activates a timer delaying connection of the board components to power until the physical connection between the card and the industrial controller has stabilized. At this time current drain is ramped up by a controlling series FET. Upon removal of the card, the power failure signal causes outputs of an on-board microprocessor to be pulled to particular states necessary to prevent disturbance of a battery backed-up RAM and to eliminate current flow through protection diodes on other memory type devices attached to the microprocessor.
摘要翻译：工业控制器的电路卡可以通过使用从卡和工业控制器之间的连接器上的缩短的引脚导出的电源故障信号而被去除或插入电力而不损失其他模块的电源的存储器或干扰。电源故障信号激活定时器延迟板组件的连接，直到卡和工业控制器之间的物理连接稳定。此时，电流漏极由控制串联FET上升。在取出卡时，电源故障信号使得车载微处理器的输出被拉到必要的特定状态，以防止电池备份的RAM的干扰，并消除电流流经其它存储器类型的设备上的保护二极管微处理器。

2. 发明授权

US6018797A Integrated relay ladder language, reduced instruction set computer 失效
标题翻译：集成式梯形图语言，精简指令集电脑
公开(公告)号：US6018797A
公开(公告)日：2000-01-25
申请号：US987033
申请日：1997-12-09
申请人： Otomar Schmidt , Richard S. Gunsaulus , Ronald E. Schultz , Jeffery W. Brooks
发明人： Otomar Schmidt , Richard S. Gunsaulus , Ronald E. Schultz , Jeffery W. Brooks
IPC分类号： G06F15/78
CPC分类号： G05B19/052 , G06F9/30094 , G06F9/30181 , G06F9/30189 , G05B2219/15061 , G05B2219/15127
摘要： An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.
摘要翻译：集成RISC和继电器梯形图逻辑处理器使用共享寄存器，程序计数器，总线和处理电路来消除与协处理器类型架构中的控制传输相关的延迟。 RISC指令不会显着干扰快速继电器逻辑执行所需的专用硬件，后者可通过使用非常适合于创建少量管道危险的梯形图梯形逻辑的管道进一步改进。用于算术和逻辑指令的两个级别的条件代码允许嵌套算术运算，而不会干扰用户可见的那些指令。提供混合指令以使梯形图指令与算术指令同步，从而真正集成两个指令集。

3. 发明授权

US5619409A Program analysis circuitry for multi-tasking industrial controller 失效
标题翻译：用于多任务工业控制器的程序分析电路
公开(公告)号：US5619409A
公开(公告)日：1997-04-08
申请号：US489422
申请日：1995-06-12
申请人： Ronald E. Schultz , Charles M. Rischar , Richard S. Gunsaulus , Otomar Schmidt
发明人： Ronald E. Schultz , Charles M. Rischar , Richard S. Gunsaulus , Otomar Schmidt
IPC分类号： G06F9/48 , G06F19/00 , G06F9/46
CPC分类号： G06F9/4812
摘要： A multi-tasking industrial controller for real-time control of machinery and the like permits the use of both periodic and event driven tasks by establishing a hierarchy of both task types in the form of priorities that resolve conflicts between events of the same and different types. Each task may access a common "global" memory area to communicate information and timing with other tasks and so as to coordinate the overall industrial control process. Trouble-shooting of the task software is made possible by a hardware address monitor which may be programmed to identify access of a particular memory location or range by any task and to record information about the particular task causing that global memory access.
摘要翻译：用于机械等的实时控制的多任务工业控制器允许通过以解决相同和不同类型的事件之间的冲突的优先级的形式来建立两个任务类型的层次结构来允许周期性和事件驱动的任务的使用。每个任务可以访问一个共同的“全局”存储器区域，以便与其他任务进行信息和时序通信，以便协调整个工业控制过程。可以通过硬件地址监视器来对任务软件进行故障排除，硬件地址监视器可以被编程为通过任何任务来识别特定存储器位置或范围的访问，并且记录关于导致全局存储器访问的特定任务的信息。

4. 发明授权

US5715439A Bi-directional co-processor interface 失效
标题翻译：双向协处理器接口
公开(公告)号：US5715439A
公开(公告)日：1998-02-03
申请号：US762650
申请日：1996-12-09
申请人： Otomar Schmidt , Richard S. Gunsaulus , Ronald E. Schultz , Charles M. Rischar , Jeffrey W. Brooks
发明人： Otomar Schmidt , Richard S. Gunsaulus , Ronald E. Schultz , Charles M. Rischar , Jeffrey W. Brooks
IPC分类号： G05B19/05 , G06F9/38 , G06F9/42 , G06F9/455
CPC分类号： G06F9/4426 , G05B19/052 , G06F9/3879 , G06F9/3881 , G05B2219/15127
摘要： A co-processor interface allows both a general processor and a relay ladder processor to make repeated calls to each other in the execution of subroutines. A register transfer instruction detected by the relay ladder processor triggers a suspension of the general processor. Return of control to the general processor is accomplished at the same time a register value is provided to the general processor that the general processor uses to reinitialize its program counter. For most single level transfers of control, a single transition instruction between the general processor to the relay ladder processor is sufficient to perform a call.
摘要翻译：协处理器接口允许通用处理器和梯形图处理器在执行子程序时相互重复调用。由梯形图处理器检测到的寄存器传送指令触发了通用处理器的暂停。将控制返回到通用处理器是在通用处理器使用来重新初始化其程序计数器的同时向通用处理器提供寄存器值的同时完成的。对于大多数单级控制传输，通用处理器与梯形图梯形图处理器之间的单个转换指令足以执行调用。

5. 发明授权

US5781776A Industrial controller permitting program editing during program execution 失效
标题翻译：工业控制器允许在程序执行期间编辑程序
公开(公告)号：US5781776A
公开(公告)日：1998-07-14
申请号：US551441
申请日：1995-11-01
申请人： David A. Johnston , Charles M. Rischar , Ronald E. Schultz , Otomar Schmidt
发明人： David A. Johnston , Charles M. Rischar , Ronald E. Schultz , Otomar Schmidt
IPC分类号： G06F9/445 , G06F9/44
CPC分类号： G05B19/056 , G06F8/67 , G05B2219/13153
摘要： A method of editing a real-time control program as it controls equipment is provided in which the editing occurs in a second area of memory and integrated into the pre-existing program by means of conditional jump instructions concatenated to that edited material. The pre-existing program is uninterrupted by the editing process except for a change of single instructions which do not affect the results of the execution but redirect the execution thread of that control program to be conditionally connected to the edited material. This single writing of single instructions, which do not affect execution results, precludes the possibility of the controller executing partially edited programs. The jump instructions are conditional on a test edit pointer to allow instantaneous implementation of the edits and a simple return to unedited instructions simply by changing the state of the flag.
摘要翻译：提供了一种在控制设备时编辑实时控制程序的方法，其中编辑发生在存储器的第二区域中，并通过连接到编辑的材料的条件跳转指令将其集成到预先存在的程序中。编辑过程中不存在预先存在的程序，除了改变不影响执行结果的单个指令，而是将控制程序的执行线程重定向到有条件地连接到编辑的材料。单个指令的单写不影响执行结果，排除了控制器执行部分编辑程序的可能性。跳转指令以测试编辑指针为条件，以允许即时实现编辑，并简单地通过更改标志的状态简单地返回到未编辑的指令。

6. 发明授权

US4638452A Programmable controller with dynamically altered programmable real time interrupt interval 失效
标题翻译：可编程控制器，具有动态改变的可编程实时中断间隔
公开(公告)号：US4638452A
公开(公告)日：1987-01-20
申请号：US584128
申请日：1984-02-27
申请人： Ronald E. Schultz , Otomar Schmidt , David A. Johnston
发明人： Ronald E. Schultz , Otomar Schmidt , David A. Johnston
IPC分类号： G05B19/05 , G06F15/18
CPC分类号： G05B19/05 , G05B2219/13001 , G05B2219/15052 , G05B2219/15079 , G05B2219/15081
摘要： A programmable controller includes a main processor which executes a user control program. The main processor is interrupted by a support processor which operates as a real time clock. The interval between interrupts is determined by instructions within the user control program and may be dynamically altered when required. The main processor executes a user created interrupt routine when each interrupt occurs.
摘要翻译：可编程控制器包括执行用户控制程序的主处理器。主处理器被作为实时时钟操作的支持处理器中断。中断之间的间隔由用户控制程序内的指令确定，并且可以在需要时动态地改变。当每个中断发生时，主处理器执行用户创建的中断程序。

7. 发明授权

US4165534A Digital control system with Boolean processor 失效
标题翻译：具有布尔处理器的数字控制系统
公开(公告)号：US4165534A
公开(公告)日：1979-08-21
申请号：US911520
申请日：1978-06-01
申请人： Ernst Dummermuth , Raymond A. Grudowski , Valdis Grants , Otomar Schmidt
发明人： Ernst Dummermuth , Raymond A. Grudowski , Valdis Grants , Otomar Schmidt
IPC分类号： G05B19/05 , G05B11/01 , G05B19/02 , G06F9/06
CPC分类号： G05B19/052 , G05B2219/1103 , G05B2219/1159 , G05B2219/1204 , G05B2219/13128 , G05B2219/15048 , G05B2219/15127
摘要： An eight-bit microprocessor sequentially reads controller type instructions from a memory and applies the operation codes of selected ones of the instructions to a hardwired Boolean processor. The microprocessor also couples status words between an I/O image table stored in the memory and the I/O interface racks which connect the programmable controller to the machine being controlled. In general, those controller type instructions which are word oriented are executed by the microprocessor and those which are single-bit oriented are executed by the Boolean processor. The Boolean processor is operable in combination with the microprocessor to examine selected status bits in the I/O image table and to set selected status bits therein to a logic state which is determined in part by the state of the examined status bits.
摘要翻译： 8位微处理器从存储器中顺序读取控制器类型的指令，并将所选指令的操作代码应用到硬连线布尔处理器。微处理器还将存储在存储器中的I / O映像表和将可编程控制器连接到被控制的机器的I / O接口机架之间的状态字进行耦合。通常，面向对象的那些控制器类型指令由微处理器执行，并且由单位定向的那些指令由布尔处理器执行。布尔处理器与微处理器结合操作以检查I / O映像表中的所选状态位，并将其中的选定状态位设置为部分由被检查状态位的状态确定的逻辑状态。

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