专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5914970A Computer memory system providing parity with standard non-parity memory devices 失效
标题翻译：计算机存储系统与标准非奇偶校验存储器件提供奇偶校验
公开(公告)号：US5914970A
公开(公告)日：1999-06-22
申请号：US921730
申请日：1997-08-27
申请人： Richard S. Gunsaulus , Otomar S. Schmidt
发明人： Richard S. Gunsaulus , Otomar S. Schmidt
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： G06F11/1044
摘要： A memory system uses standard memory devices not normally supporting parity bits. Parity bits for multiple memory devices are stored in a dedicated parity device shared among multiple memory devices. Inadvertent erasure of the parity information, when writing to a single memory device, is prevented by a prereading of the parity device prior to a writing to the single memory device. Special circuitry stores the preread parity information and merges it back with the calculated parity bit for the written data to preserve complete parity information.
摘要翻译：存储器系统使用通常不支持奇偶校验位的标准存储器件。用于多个存储器设备的奇偶校验位存储在多个存储器件之间共享的专用奇偶校验设备中。在向单个存储器件写入时，奇偶校验信息的无意擦除被防止在对单个存储器件的写入之前奇偶校验器件的预读写。特殊电路存储预读奇偶校验信息，并将其与编写的数据的计算奇偶校验位合并，以保留完整的奇偶校验信息。

2. 发明授权

US5715439A Bi-directional co-processor interface 失效
标题翻译：双向协处理器接口
公开(公告)号：US5715439A
公开(公告)日：1998-02-03
申请号：US762650
申请日：1996-12-09
申请人： Otomar Schmidt , Richard S. Gunsaulus , Ronald E. Schultz , Charles M. Rischar , Jeffrey W. Brooks
发明人： Otomar Schmidt , Richard S. Gunsaulus , Ronald E. Schultz , Charles M. Rischar , Jeffrey W. Brooks
IPC分类号： G05B19/05 , G06F9/38 , G06F9/42 , G06F9/455
CPC分类号： G06F9/4426 , G05B19/052 , G06F9/3879 , G06F9/3881 , G05B2219/15127
摘要： A co-processor interface allows both a general processor and a relay ladder processor to make repeated calls to each other in the execution of subroutines. A register transfer instruction detected by the relay ladder processor triggers a suspension of the general processor. Return of control to the general processor is accomplished at the same time a register value is provided to the general processor that the general processor uses to reinitialize its program counter. For most single level transfers of control, a single transition instruction between the general processor to the relay ladder processor is sufficient to perform a call.
摘要翻译：协处理器接口允许通用处理器和梯形图处理器在执行子程序时相互重复调用。由梯形图处理器检测到的寄存器传送指令触发了通用处理器的暂停。将控制返回到通用处理器是在通用处理器使用来重新初始化其程序计数器的同时向通用处理器提供寄存器值的同时完成的。对于大多数单级控制传输，通用处理器与梯形图梯形图处理器之间的单个转换指令足以执行调用。

3. 发明授权

US5027317A Method and circuit for limiting access to a RAM program memory 失效
标题翻译：用于限制对RAM程序存储器的访问的方法和电路
公开(公告)号：US5027317A
公开(公告)日：1991-06-25
申请号：US325454
申请日：1989-03-17
申请人： Gerald S. Pepera , Richard S. Gunsaulus
发明人： Gerald S. Pepera , Richard S. Gunsaulus
IPC分类号： G06F12/14
CPC分类号： G06F12/1433
摘要： A method and a circuit limit access to a locked portion of memory to periods when application program instructions in the locked portion of memory are being executed. An UNLOCK routine of processor instructions is executed before accessing the portion of the memory storing the application program instructions and a LOCK routine of processor instructions is executed to re-secure the memory after such access. The locking and unlocking is accomplished by addressing a comparator and transmitting data representing either a lock value or an unlock value. The comparator is connected to enable and disable decoding circuitry which in turn controls access to the locked portion of memory.
摘要翻译：一种方法和电路限制对存储器的锁定部分的访问，以及正在执行存储器的锁定部分中的应用程序指令的时期。在访问存储应用程序指令的存储器的部分之前执行处理器指令的解锁程序，并且执行处理器指令的LOCK例程以在这样的访问之后重新保护存储器。锁定和解锁通过寻址比较器并发送表示锁定值或解锁值的数据来实现。比较器被连接以启用和禁用解码电路，其又控制对存储器的锁定部分的访问。

4. 发明授权

US6018797A Integrated relay ladder language, reduced instruction set computer 失效
标题翻译：集成式梯形图语言，精简指令集电脑
公开(公告)号：US6018797A
公开(公告)日：2000-01-25
申请号：US987033
申请日：1997-12-09
申请人： Otomar Schmidt , Richard S. Gunsaulus , Ronald E. Schultz , Jeffery W. Brooks
发明人： Otomar Schmidt , Richard S. Gunsaulus , Ronald E. Schultz , Jeffery W. Brooks
IPC分类号： G06F15/78
CPC分类号： G05B19/052 , G06F9/30094 , G06F9/30181 , G06F9/30189 , G05B2219/15061 , G05B2219/15127
摘要： An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.
摘要翻译：集成RISC和继电器梯形图逻辑处理器使用共享寄存器，程序计数器，总线和处理电路来消除与协处理器类型架构中的控制传输相关的延迟。 RISC指令不会显着干扰快速继电器逻辑执行所需的专用硬件，后者可通过使用非常适合于创建少量管道危险的梯形图梯形逻辑的管道进一步改进。用于算术和逻辑指令的两个级别的条件代码允许嵌套算术运算，而不会干扰用户可见的那些指令。提供混合指令以使梯形图指令与算术指令同步，从而真正集成两个指令集。

5. 发明授权

US5619409A Program analysis circuitry for multi-tasking industrial controller 失效
标题翻译：用于多任务工业控制器的程序分析电路
公开(公告)号：US5619409A
公开(公告)日：1997-04-08
申请号：US489422
申请日：1995-06-12
申请人： Ronald E. Schultz , Charles M. Rischar , Richard S. Gunsaulus , Otomar Schmidt
发明人： Ronald E. Schultz , Charles M. Rischar , Richard S. Gunsaulus , Otomar Schmidt
IPC分类号： G06F9/48 , G06F19/00 , G06F9/46
CPC分类号： G06F9/4812
摘要： A multi-tasking industrial controller for real-time control of machinery and the like permits the use of both periodic and event driven tasks by establishing a hierarchy of both task types in the form of priorities that resolve conflicts between events of the same and different types. Each task may access a common "global" memory area to communicate information and timing with other tasks and so as to coordinate the overall industrial control process. Trouble-shooting of the task software is made possible by a hardware address monitor which may be programmed to identify access of a particular memory location or range by any task and to record information about the particular task causing that global memory access.
摘要翻译：用于机械等的实时控制的多任务工业控制器允许通过以解决相同和不同类型的事件之间的冲突的优先级的形式来建立两个任务类型的层次结构来允许周期性和事件驱动的任务的使用。每个任务可以访问一个共同的“全局”存储器区域，以便与其他任务进行信息和时序通信，以便协调整个工业控制过程。可以通过硬件地址监视器来对任务软件进行故障排除，硬件地址监视器可以被编程为通过任何任务来识别特定存储器位置或范围的访问，并且记录关于导致全局存储器访问的特定任务的信息。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式