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1. 发明授权

US06583445B1 Integrated electronic-optoelectronic devices and method of making the same 有权
标题翻译：集成电子光电器件及其制作方法
公开(公告)号：US06583445B1
公开(公告)日：2003-06-24
申请号：US09658259
申请日：2000-09-08
申请人： Ronald E. Reedy , Ravindra A. Athale , George J. Simonis , Andreas G. Andreou , Alyssa Apsel , Zaven Kalayjian , Philippe O. Pouliquen
发明人： Ronald E. Reedy , Ravindra A. Athale , George J. Simonis , Andreas G. Andreou , Alyssa Apsel , Zaven Kalayjian , Philippe O. Pouliquen
IPC分类号： H01L2715
CPC分类号： H01L31/101 , H01L2924/0002 , H01S5/021 , H01S5/02272 , H01S5/0261 , H01S5/0262 , H01S5/0265 , H01S5/183 , H01L2924/00
摘要： An integrated electronic-optoelectronic module comprising: an ultrathin silicon-on-sapphire composite substrate; at least one electronic device fabricated in the ultrathin silicon; and at least one optoelectronic device bonded to the ultrathin silicon-on-sapphire composite substrate and in electrical communication with the at least one electronic device fabricated in the ultrathin silicon layer. For example, VCSELs and photodetectors are integrated with CMOS electronic circuitry to provide useful modules for electro-optical interconnects for computing and switching systems.
摘要翻译：一种集成电子光电模块，包括：超薄蓝宝石蓝宝石复合衬底; 至少一个以超薄硅制造的电子器件; 以及至少一个光电子器件，其结合到超薄蓝宝石蓝宝石复合衬底上并且与在超薄硅层中制造的至少一个电子器件电连通。例如，VCSEL和光电检测器与CMOS电子电路集成，为计算和交换系统的电光互连提供有用的模块。

2. 发明申请

US20170131143A1 PHOTODETECTION CIRCUIT AND OPERATING METHOD THEREOF 有权
公开(公告)号：US20170131143A1
公开(公告)日：2017-05-11
申请号：US15318373
申请日：2014-07-02
申请人： Andreas G. ANDREOU , Joseph H. LIN , Philippe O. POULIQUEN , Charbel G. RIZK , The Johns Hopkins University
发明人： Andreas G. Andreou , Joseph H. Lin , Philippe O. Pouliquen , Charbel G. Rizk
IPC分类号： G01J1/44 , H01L31/02 , H01L31/0352 , H01L31/107
CPC分类号： G01J1/44 , G01J2001/4406 , G01J2001/442 , G01J2001/4466 , G01J2001/448 , H01L31/02027 , H01L31/035272 , H01L31/107
摘要： A photodetection circuit includes an avalanche photodiode and a mode switching circuit that may be configured to selectively switch an operating mode of the photodetection circuit between linear mode and Geiger mode. The photodetection circuit may further include a quenching circuit configured to quench and reset the avalanche photodiode in response to an avalanche event when the photodetection circuit is operated in Geiger mode. The photodetection circuit may additionally include an integration circuit configured to integrate photocurrent output by the photodiode and generate integrated charge units when the photodetection circuit is operated in linear mode. The photodetection circuit may also include a counter configured to count pulses output by the avalanche photodiode when the photodetection circuit is operated in Geiger mode and to count integrated charge units generated by the integration circuit when the photodetection circuit is operated in linear mode.

3. 发明授权

US08259293B2 Deep submicron and nano CMOS single photon photodetector pixel with event based circuits for readout data-rate reduction communication system 有权
标题翻译：深亚微米和纳米CMOS单光子光电检测器像素，具有用于读出数据速率降低通信系统的基于事件的电路
公开(公告)号：US08259293B2
公开(公告)日：2012-09-04
申请号：US12531191
申请日：2008-03-17
申请人： Andreas G. Andreou , Miriam Adlerstein Marwick , Philippe O. Pouliquen
发明人： Andreas G. Andreou , Miriam Adlerstein Marwick , Philippe O. Pouliquen
IPC分类号： G01J1/42
CPC分类号： H01L27/14603 , H01L31/107
摘要： An avalanche photodiode is disclosed. The avalanche photodiode includes a substrate of a first conductivity type. A first well of a second conductivity type is formed within the substrate. A second well of the second conductivity type is formed substantially overlying and extending into the first well. A heavily doped region of the first conductivity type is formed substantially overlying and extending into the first well, the junction between the heavily doped region and the second well forming an avalanche multiplication region. A guard ring is formed from a first conductivity material positioned substantially about the periphery of the multiplication region at least partially underlying the heavily doped region. An outer well ring of the second conductivity type is formed about the perimeter of the deep well and the guard ring.
摘要翻译：公开了一种雪崩光电二极管。雪崩光电二极管包括第一导电类型的衬底。在衬底内形成第二导电类型的第一阱。第二导电类型的第二阱基本上覆盖并延伸到第一阱中。第一导电类型的重掺杂区基本上覆盖并延伸到第一阱中，重掺杂区和第二阱之间的结形成雪崩倍增区。保护环由第一导电材料形成，该第一导电材料基本上位于至少部分地位于重掺杂区域下方的乘法区域的周边。围绕深井和保护环的周边形成第二导电类型的外井环。

4. 发明申请

US20100245809A1 DEEP SUBMICRON AND NANO CMOS SINGLE PHOTON PHOTODETECTOR PIXEL WITH EVENT BASED CIRCUITS FOR READOUT DATA-RATE REDUCTION COMMUNICATION SYSTEM 有权
标题翻译： DEEP SUBMICRON和NANO CMOS单根光电子像素与基于事件的电路，用于读取数据速率减少通信系统
公开(公告)号：US20100245809A1
公开(公告)日：2010-09-30
申请号：US12531191
申请日：2008-03-17
申请人： Andreas G. Andreou , Miriam Adlerstein Marwick , Philippe O. Pouliquen
发明人： Andreas G. Andreou , Miriam Adlerstein Marwick , Philippe O. Pouliquen
IPC分类号： H01L27/144 , H01L31/107 , G01J1/44
CPC分类号： H01L27/14603 , H01L31/107
摘要： An avalanche photodiode and a sensor array comprising an array of said avalanche photodiodes is disclosed. Then avalanche photodiode comprises a substrate of a first conductivity type; a first well of a second conductivity type formed within the substrate; a second well of the second conductivity type formed substantially overlying and extending into the first well; a heavily doped region of the first conductivity type formed substantially overlying and extending into the first well, the junction between the heavily doped region and the second well forming an avalanche multiplication region; a guard ring formed from a first conductivity material positioned substantially about the periphery of the multiplication region at least partially underlying the heavily doped region; and an outer well ring of the second conductivity type formed about the perimeter of the deep well and the guard ring. The sensor array comprises a plurality of pixel elements, each of the pixel elements being configured to operate on discrete value continuous time (DVCT) basis. Each of the pixel elements can include the avalanche photodiode previously described.
摘要翻译：公开了一种雪崩光电二极管和包括所述雪崩光电二极管阵列的传感器阵列。然后雪崩光电二极管包括第一导电类型的衬底; 在衬底内形成的第二导电类型的第一阱; 第二导电类型的第二阱基本上覆盖并延伸到第一阱中; 第一导电类型的重掺杂区域基本上覆盖并延伸到第一阱中，重掺杂区域和形成雪崩倍增区域的第二阱之间的结; 由第一导电材料形成的保护环，该第一导电材料基本上围绕至少部分地位于重掺杂区域下方的倍增区域的周边; 以及围绕深井和保护环的周边形成的第二导电类型的外阱环。传感器阵列包括多个像素元件，每个像素元件被配置为基于离散值连续时间（DVCT）进行操作。每个像素元件可以包括先前描述的雪崩光电二极管。

5. 发明授权

US5206541A Current-mode based analog circuits for synthetic neural systems 失效
标题翻译：用于合成神经系统的电流模式模拟电路
公开(公告)号：US5206541A
公开(公告)日：1993-04-27
申请号：US693310
申请日：1991-04-30
申请人： Kwabena A. Boahen , Andreas G. Andreou , Philippe O. Pouliquen , Robert E. Jenkins
发明人： Kwabena A. Boahen , Andreas G. Andreou , Philippe O. Pouliquen , Robert E. Jenkins
IPC分类号： G06N3/063
CPC分类号： G06N3/0635
摘要： A two transistor current-controlled current conveyor (C4) circuit is provided which exploits the translinear properties of the MOS transistor in subthreshold and uses unidirectional current signals. As a result, the circuits of the invention achieve high functionality and integration density with very low power dissipation. Two C4 circuits connected to and communicating through a bidirectional junction circuit of the invention permit the transmission of independent, bidirectional signals. These circuits are useful for implementing synthetic neural systems such as associative memories and silicon retinas, such as winner-takes-all and pyramidal neuron circuits and the outer-plexiform layer of a retina.
摘要翻译：提供了两个晶体管电流控制电流输送机（C4）电路，其利用亚阈值下的MOS晶体管的跨导特性，并使用单向电流信号。结果，本发明的电路以非常低的功耗实现了高功能性和集成密度。通过本发明的双向结电路连接和通信的两个C4电路允许传输独立的双向信号。这些电路对于实现诸如关联记忆和硅视网膜之类的合成神经系统是有用的，例如获胜者全部和锥体神经元电路以及视网膜的外丛状层。

6. 发明授权

US06720830B2 Low-power, differential optical receiver in silicon on insulator 失效
标题翻译：低功耗，差分光接收器在硅绝缘体上
公开(公告)号：US06720830B2
公开(公告)日：2004-04-13
申请号：US10166052
申请日：2002-06-11
申请人： Andreas G. Andreou , Alyssa Apsel
发明人： Andreas G. Andreou , Alyssa Apsel
IPC分类号： H03F345
CPC分类号： H03F3/45183 , H03F3/082 , H03F3/45475 , H03F2203/45601 , H03F2203/45631 , H03F2203/45644 , H03F2203/45698
摘要： A low-power differential optical receiver useful for high-speed optical communication between CMOS chips includes a multi-stage differential amplifier circuit including a first differential transimpedance stage (22) followed by a plurality of differential feed-forward, high-bandwidth gain stages (24) and a final, differential-to-single-ended converter output stage (26). The inputs of the transimpedance stage receive input signals from a MSM or PIN diode photo-detector. Transistors having plural, different threshold levels are employed within each differential amplifier stage to reduce the size of the footprint of the circuit and improve the gain and bandwidth while decreasing the parasitic capacitance. The optical receiver is fabricated on a silicon on insulator chip, such as in an ultra-thin silicon on sapphire CMOS process which enables the design of high speed circuits with low power consumption and no substrate cross-talk. The circuit design is well-suited for use in a multi-dimensional array of optical interconnects between CMOS chips or platforms.
摘要翻译：用于CMOS芯片之间的高速光通信的低功率差分光接收器包括多级差分放大器电路，该多级差分放大器电路包括第一差分跨阻抗级（22），随后是多个差分前馈，高带宽增益级（ 24）和最终的差分到单端转换器输出级（26）。跨导级的输入接收来自MSM或PIN二极管光电检测器的输入信号。在每个差分放大器级中采用具有多个不同阈值电平的晶体管，以减小电路的覆盖区的尺寸，并在降低寄生电容的同时提高增益和带宽。光接收器制造在绝缘体上的芯片上，例如蓝宝石CMOS工艺中的超薄硅片，能够设计低功耗且无衬底串扰的高速电路。电路设计非常适合用于CMOS芯片或平台之间的光学互连的多维阵列。

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