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1. 发明授权

US07324525B2 Method and apparatus for coalescing acknowledge packets within a server 失效
标题翻译：在服务器内合并确认数据包的方法和装置
公开(公告)号：US07324525B2
公开(公告)日：2008-01-29
申请号：US11008799
申请日：2004-12-09
申请人： Ronald E. Fuhs , Calvin C. Paynton , Steven L. Rogers , Nathaniel P. Sellin , Scott M. Willenborg
发明人： Ronald E. Fuhs , Calvin C. Paynton , Steven L. Rogers , Nathaniel P. Sellin , Scott M. Willenborg
IPC分类号： H04L12/28 , H04L12/66
CPC分类号： H04L12/56
摘要： A method for coalescing acknowledge packets within a server is disclosed. A Read Request queue having multiple queue pair entries is provided. Each of the queue pair entries includes a packet sequence number (PSN) field and an indicator field. In response to a receipt of a Write Request packet, an indicator field of a queue pair entry is set to indicate that an Ack packet has been queued within the queue pair entry, and a PSN of the Write Request packet is written into a PSN field of the queue pair entry. In addition, a Queue Write Pointer is maintained to point to the queue pair entry. In response to a receipt of a Read Request packet, the indicator field of the queue pair entry is set to indicate that a Read Request packet has been queued within the queue pair entry, and a PSN of the Read Request packet is written into the PSN field of the queue pair entry. Also, the Queue Write Pointer is advanced to point to a queue pair entry that is subsequent to the queue pair entry.
摘要翻译：公开了一种用于在服务器内聚合确认分组的方法。提供了具有多个队列对条目的读请求队列。每个队列对条目包括分组序列号（PSN）字段和指示符字段。响应于写请求分组的接收，设置队列对条目的指示符字段以指示Ack分组已经在队列对条目中排队，并且写请求分组的PSN被写入PSN字段的队列对条目。此外，维护队列写入指针以指向队列对条目。响应于读取请求分组的接收，队列对条目的指示符字段被设置为指示读取请求分组已经在队列对条目中排队，并且读取请求分组的PSN被写入PSN 字段的队列对条目。此外，队列写入指针被提前指向队列对条目后面的队列对条目。

2. 发明授权

US08934332B2 Multi-threaded packet processing 有权
标题翻译：多线程数据包处理
公开(公告)号：US08934332B2
公开(公告)日：2015-01-13
申请号：US13408575
申请日：2012-02-29
申请人： Ronald E. Fuhs , Scott M. Willenborg
发明人： Ronald E. Fuhs , Scott M. Willenborg
IPC分类号： G06F11/00 , G01R31/08 , H04L12/24 , G06F3/00 , G06F15/00 , G06F7/38
CPC分类号： G06F9/5083 , G06F2209/509
摘要： A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A second data packet from the plurality of sequentially ordered data packets is directed to a second offload engine, wherein the second data packet is sequentially subsequent to the first data packet. The second offload engine receives information from the first offload engine, wherein the information reflects that the first offload engine is processing the first data packet. Based on the information received at the second offload engine, the second offload engine processes the second data packet so that critical events in the processing of the first data packet by the first offload engine occur prior to critical events in the processing of the second data packet by the second offload engine.
摘要翻译：公开了用于同时处理顺序敏感数据分组的系统。来自多个顺序排列的数据分组的第一数据分组被引导到第一卸载引擎。来自多个顺序排列的数据分组的第二数据分组被引导到第二卸载引擎，其中第二数据分组依次在第一数据分组之后。第二卸载引擎从第一卸载引擎接收信息，其中信息反映第一卸载引擎正在处理第一数据包。基于在第二卸载引擎处接收到的信息，第二卸载引擎处理第二数据分组，使得由第一卸载引擎处理第一数据分组的关键事件发生在第二数据分组的处理中的关键事件之前由第二个卸载引擎。

3. 发明授权

US07855954B2 Speculative credit data flow control 有权
标题翻译：投机信用数据流控制
公开(公告)号：US07855954B2
公开(公告)日：2010-12-21
申请号：US12176810
申请日：2008-07-21
申请人： Scott M. Willenborg , Ronald E. Fuhs
发明人： Scott M. Willenborg , Ronald E. Fuhs
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/11 , H04L47/2416 , H04L47/39
摘要： A method of speculative credit data flow control includes defining a low watermark value as a function of a number of open buffers in a receiving unit; receiving a data packet from a sending unit; determining whether the data packet includes a packet delay indicator; defining a first speculative credit value responsive to receiving the packet delay indicator; defining a second speculative credit value as a function of the first speculative credit value added to a regular credit value; generating a flow control packet including the second speculative credit value; and sending the flow control packet to the sending unit.
摘要翻译：推测信用数据流控制的方法包括：将接收单元中的开放缓冲器的数量定义为低水印值; 从发送单元接收数据分组; 确定所述数据分组是否包括分组延迟指示符; 响应于接收到所述分组延迟指示符定义第一推测信用值; 定义作为添加到正常信用值的第一投机信用值的函数的第二投机信用值; 生成包含第二推测信用值的流量控制包; 并将流量控制分组发送到发送单元。

4. 发明申请

US20100014421A1 SPECULATIVE CREDIT DATA FLOW CONTROL 有权
标题翻译：信用信用数据流控制
公开(公告)号：US20100014421A1
公开(公告)日：2010-01-21
申请号：US12176810
申请日：2008-07-21
申请人： Scott M. Willenborg , Ronald E. Fuhs
发明人： Scott M. Willenborg , Ronald E. Fuhs
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/11 , H04L47/2416 , H04L47/39
摘要： A method of speculative credit data flow control includes defining a low watermark value as a function of a number of open buffers in a receiving unit; receiving a data packet from a sending unit; determining whether the data packet includes a packet delay indicator; defining a first speculative credit value responsive to receiving the packet delay indicator; defining a second speculative credit value as a function of the first speculative credit value added to a regular credit value; generating a flow control packet including the second speculative credit value; and sending the flow control packet to the sending unit.
摘要翻译：推测信用数据流控制的方法包括：将接收单元中的开放缓冲器的数量定义为低水印值; 从发送单元接收数据分组; 确定所述数据分组是否包括分组延迟指示符; 响应于接收到所述分组延迟指示符定义第一推测信用值; 定义作为添加到正常信用值的第一投机信用值的函数的第二投机信用值; 生成包含第二推测信用值的流量控制包; 并将流量控制分组发送到发送单元。

5. 发明申请

US20130268700A1 PREFETCHING FOR A SHARED DIRECT MEMORY ACCESS (DMA) ENGINE 失效
标题翻译：共享直接存储器访问（DMA）引擎的预编译
公开(公告)号：US20130268700A1
公开(公告)日：2013-10-10
申请号：US13438864
申请日：2012-04-04
申请人： Ronald E. Fuhs , Scott M. Willenborg
发明人： Ronald E. Fuhs , Scott M. Willenborg
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A system is disclosed for fetching control instructions for a direct memory access (DMA) engine shared between a plurality of threads. For a data transfer from a first thread by a DMA engine, the DMA engine fetches and processes a predetermined number of control instructions (or work queue elements) for the data transfer, each of the control instructions including an amount and location of data to transfer. The DMA engine determines a total amount of data transferred as a result of the data transfer. The DMA engine then determines a difference between the total amount of data transferred and a threshold amount of data, wherein the threshold amount of data indicates a preferred amount of data to be transferred for the first thread. The predetermined number of control instructions to fetch is updated based on the determined difference.
摘要翻译：公开了一种用于获取用于在多个线程之间共享的直接存储器访问（DMA）引擎的控制指令的系统。对于由DMA引擎从第一线程进行的数据传输，DMA引擎提取并处理用于数据传送的预定数量的控制指令（或工作队列元素），每个控制指令包括要传送的数据的量和位置。 DMA引擎确定由于数据传输而传输的总数据量。 DMA引擎然后确定传送的数据总量与阈值数据量之间的差异，其中阈值数据量指示要传送给第一线程的优选数据量。基于所确定的差异来更新提取的预定数量的控制指令。

6. 发明申请

US20130223234A1 MULTI-THREADED PACKET PROCESSING 有权
标题翻译：多线程分组处理
公开(公告)号：US20130223234A1
公开(公告)日：2013-08-29
申请号：US13408575
申请日：2012-02-29
申请人： Ronald E. Fuhs , Scott M. Willenborg
发明人： Ronald E. Fuhs , Scott M. Willenborg
IPC分类号： H04L12/56 , H04L12/26
CPC分类号： G06F9/5083 , G06F2209/509
摘要： A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A second data packet from the plurality of sequentially ordered data packets is directed to a second offload engine, wherein the second data packet is sequentially subsequent to the first data packet. The second offload engine receives information from the first offload engine, wherein the information reflects that the first offload engine is processing the first data packet. Based on the information received at the second offload engine, the second offload engine processes the second data packet so that critical events in the processing of the first data packet by the first offload engine occur prior to critical events in the processing of the second data packet by the second offload engine.
摘要翻译：公开了用于同时处理顺序敏感数据分组的系统。来自多个顺序排列的数据分组的第一数据分组被引导到第一卸载引擎。来自多个顺序排列的数据分组的第二数据分组被引导到第二卸载引擎，其中第二数据分组依次在第一数据分组之后。第二卸载引擎从第一卸载引擎接收信息，其中信息反映第一卸载引擎正在处理第一数据包。基于在第二卸载引擎处接收到的信息，第二卸载引擎处理第二数据分组，使得由第一卸载引擎处理第一数据分组的关键事件发生在第二数据分组的处理中的关键事件之前由第二个卸载引擎。

7. 发明授权

US08578069B2 Prefetching for a shared direct memory access (DMA) engine 失效
标题翻译：预取共享直接内存访问（DMA）引擎
公开(公告)号：US08578069B2
公开(公告)日：2013-11-05
申请号：US13438864
申请日：2012-04-04
申请人： Ronald E. Fuhs , Scott M. Willenborg
发明人： Ronald E. Fuhs , Scott M. Willenborg
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A system is disclosed for fetching control instructions for a direct memory access (DMA) engine shared between a plurality of threads. For a data transfer from a first thread by a DMA engine, the DMA engine fetches and processes a predetermined number of control instructions (or work queue elements) for the data transfer, each of the control instructions including an amount and location of data to transfer. The DMA engine determines a total amount of data transferred as a result of the data transfer. The DMA engine then determines a difference between the total amount of data transferred and a threshold amount of data, wherein the threshold amount of data indicates a preferred amount of data to be transferred for the first thread. The predetermined number of control instructions to fetch is updated based on the determined difference.
摘要翻译：公开了一种用于获取用于在多个线程之间共享的直接存储器访问（DMA）引擎的控制指令的系统。对于由DMA引擎从第一线程进行的数据传输，DMA引擎提取并处理用于数据传送的预定数量的控制指令（或工作队列元素），每个控制指令包括要传送的数据的量和位置。 DMA引擎确定由于数据传输而传输的总数据量。 DMA引擎然后确定传送的数据总量与阈值数据量之间的差异，其中阈值数据量指示要传送给第一线程的优选数据量。基于所确定的差异来更新提取的预定数量的控制指令。

8. 发明授权

US07366813B2 Event queue in a logical partition 有权
标题翻译：逻辑分区中的事件队列
公开(公告)号：US07366813B2
公开(公告)日：2008-04-29
申请号：US11764988
申请日：2007-06-19
申请人： Thomas A. Gregg , Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Steven L. Rogers , Donald W. Schmidt , Bruce M. Walk
发明人： Thomas A. Gregg , Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Steven L. Rogers , Donald W. Schmidt , Bruce M. Walk
IPC分类号： G06F13/24 , G06F3/00 , G06F13/40
CPC分类号： G06F9/546 , G06F2209/548 , H04L49/901
摘要： An information processing system is provided which includes a plurality of system resources, and an event queue having a predetermined number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.
摘要翻译：提供了包括多个系统资源的信息处理系统和具有预定数量的条目的事件队列。信息处理系统的事件记录机制可操作用于对事件队列中的事件进行条目，其中每个系统资源每个事件类型事件限制事件队列中预定数量的活动条目。在特定实施例中，每个系统资源的每种类型的事件的条目数量被限制为一个。

9. 发明授权

US5469446A Retry filter and circulating echo method and apparatus 失效
标题翻译：重试过滤器和循环回波方法和装置
公开(公告)号：US5469446A
公开(公告)日：1995-11-21
申请号：US187693
申请日：1994-01-26
申请人： Ronald E. Fuhs , William A. Hammond, Jr. , George W. Nation , Steven L. Rogers , John C. Willis
发明人： Ronald E. Fuhs , William A. Hammond, Jr. , George W. Nation , Steven L. Rogers , John C. Willis
IPC分类号： G08C25/02 , H04L1/00 , H04L1/18 , H04L12/42 , H04L1/20
CPC分类号： H04L12/42 , G08C25/02 , H04L1/187 , H04L1/1848 , H04L1/188 , H04L2001/0095
摘要： A retry filter and circulating echo apparatus and method are provided for a digital processing system of the type having multiple nodes that communicate via one or more unidirectional rings. The nodes of a digital processing system communicate packets to each other over a unidirectional ring bus. An origination node allocates a sequence identification and transmits a packet to a destination node, which generates a first echo packet and also sets a packet filter indication to drop any further copies of that packet. The first echo packet is sent to the origination node as a confirmation. The origination node generates a second echo packet and sends the generated second echo packet onward to the destination node again as an indication that the packet will not be retransmitted. The destination node transmits a third echo packet as an indication that the sequence can be deallocated.
摘要翻译：为具有经由一个或多个单向环通信的多个节点的类型的数字处理系统提供了重试过滤器和循环回波装置和方法。数字处理系统的节点通过单向环形总线彼此传送数据包。始发节点分配序列标识并将分组发送到目的地节点，该目的节点生成第一回波分组，并且还设置分组过滤器指示以丢弃该分组的任何其它副本。将第一个回波包作为确认发送到始发节点。始发节点生成第二回波分组，并将生成的第二回波分组再次发送到目的地节点，作为不重发分组的指示。目的地节点发送第三回波分组作为可以释放序列的指示。

10. 发明授权

US07895383B2 Event queue in a logical partition 有权
标题翻译：逻辑分区中的事件队列
公开(公告)号：US07895383B2
公开(公告)日：2011-02-22
申请号：US12043361
申请日：2008-03-06
申请人： Thomas A. Gregg , Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Steven L. Rogers , Donald W. Schmidt , Bruce M. Walk
发明人： Thomas A. Gregg , Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Steven L. Rogers , Donald W. Schmidt , Bruce M. Walk
IPC分类号： G06F13/24 , G06F3/00 , G06F13/40
CPC分类号： G06F9/546 , G06F2209/548 , H04L49/901
摘要： An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.
摘要翻译：提供了包括多个系统资源的信息处理系统和具有最大数量的条目的事件队列。信息处理系统的事件记录机制可操作用于对事件队列中的事件进行条目，其中每个系统资源每个事件类型事件限制事件队列中预定数量的活动条目。在特定实施例中，每个系统资源的每种类型的事件的条目数量被限制为一个。

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