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1. 发明授权

US4028731A Apparatus for compression coding using cross-array correlation between two-dimensional matrices derived from two-valued digital images 失效
标题翻译：使用从二值数字图像导出的二维矩阵之间的交叉阵列相关的压缩编码装置
公开(公告)号：US4028731A
公开(公告)日：1977-06-07
申请号：US617906
申请日：1975-09-29
申请人： Ronald Barthold Arps , Lalit Rai Bahl , Arnold Weinberger
发明人： Ronald Barthold Arps , Lalit Rai Bahl , Arnold Weinberger
IPC分类号： H03M7/00 , G06T9/00 , H03M7/30 , H04B1/66 , H04N1/417 , H04N7/32 , H04N7/12
CPC分类号： G06T9/005 , G06T9/004 , H04N1/417
摘要： An apparatus is disclosed for compressing a p .times. q image array of two-valued (black/white) sample points. The image array points are serially applied to the apparatus in consecutive raster scan lines. In response, the apparatus simultaneously forms two matrices respectively representing a high order p .times. q predictive error array and a p .times. q array of location events (such as the raster leading edges of all objects in the image). Improved compression is achieved by selecting between the more compression efficient of two methods for encoding the position of errors in the prediction error array. These alternative methods are conventional run-length coding and a novel form of reference encoding, used selectively but to significant advantage. Thus, a run-length compression codeword is formed from the count C of non-errors between consecutive errors (in response to the occurrence of each error in the jth bit position of the ith scan line of the predictive error array) upon either C.ltoreq.T, where T is a threshold, or C>T and there being no occurrence of a line difference encoding for the error (where i, j, C and T have positive integers). A line difference codeword with difference value v is generated upon the joint event of C>T and either the single or multiple occurrence of location events in the ith-1 scan line of the location event array within the bit position range of B.ltoreq.r.ltoreq.(j+n), where positive integer B is the greater of function D(T,v) and (j-n), and the number of intervening location events, s, within the bit position range of D(T,v).ltoreq.q
摘要翻译：公开了用于压缩二值（黑/白）采样点的p×q图像阵列的装置。图像阵列点在连续的光栅扫描线中串行地应用于设备。作为响应，装置同时形成分别表示高阶p×q预测误差阵列和位置事件的p×q阵列（诸如图像中的所有对象的光栅前沿）的两个矩阵。通过在预测误差阵列中编码错误位置的两种方法的更高的压缩效率之间进行选择来实现改进的压缩。这些替代方法是常规的游程长度编码和一种新颖的参考编码形式，其选择性使用，但具有显着的优点。因此，从C连续错误之间的非错误的计数C（响应于预测误差阵列的第i个扫描线的第j位位置中的每个错误的出现）而形成游程长度压缩码字， / = T，其中T是阈值，或C> T，并且不存在用于错误的行差编码（其中i，j，C和T具有正整数）。在C> T的联合事件处产生具有差值v的线差码字，并且在位置事件阵列的位置事件阵列的位置事件阵列的单个或多个位置事件中的单个或多个发生位置位置范围B < 其中正整数B是函数D（T，v）和（jn）中的较大者，D（T，V）和（jn）的位位置范围内的中间位置事件数s v）

2. 发明授权

US3975623A Logic array with multiple readout tables 失效
标题翻译：具有多个读出表的逻辑阵列
公开(公告)号：US3975623A
公开(公告)日：1976-08-17
申请号：US537217
申请日：1974-12-30
申请人： Arnold Weinberger
发明人： Arnold Weinberger
IPC分类号： G11C17/00 , H03K17/00 , H03K19/177 , H03K19/20
CPC分类号： H03K19/17708
摘要： This specification describes a programmable logic array (PLA) in which the readout table or OR array for the PLA is broken into two segments and the segments placed on opposite sides of the search table or AND array for the PLA. The output lines for the AND array can then be split so that outputs on one segment of those lines are fed to the OR array on one side and outputs on the other portion of those lines are fed to the OR array on the opposite side. Likewise the output lines in the OR arrays can be broken so that different functions can be fed out to opposite sides of the OR arrays. It is also possible to break input lines in both the OR and AND arrays to isolate functions from one another.
摘要翻译：该规范描述了可编程逻辑阵列（PLA），其中PLA的读出表或OR阵列被分成两个段，并且将段放置在搜索表的对侧或用于PLA的AND阵列的相对侧。然后，可以分离AND阵列的输出线，使得这些线的一个段上的输出在一侧馈送到OR阵列，并将这些线的另一部分上的输出馈送到相对侧的OR阵列。同样地，OR阵列中的输出行也可以被破坏，从而可以将不同的函数输出到OR阵列的相对侧。也可以中断OR和AND数组中的输入行，以隔离函数。

3. 发明授权

US5907671A Fault tolerant system based on voting 失效
标题翻译：基于投票的容错系统
公开(公告)号：US5907671A
公开(公告)日：1999-05-25
申请号：US700343
申请日：1996-09-23
申请人： Chin-Long Chen , Canh Xuan Le , Tin-Chee Lo , Arnold Weinberger
发明人： Chin-Long Chen , Canh Xuan Le , Tin-Chee Lo , Arnold Weinberger
IPC分类号： G06F11/10 , G06F11/18 , G06F11/00
CPC分类号： G06F11/183 , G06F11/1032
摘要： A fault tolerant circuit having improved error correction and detection properties takes advantage of two distinct forms of information redundancy: modular redundancy and parity check bit redundancy, in a cooperative fashion. In particular, it is shown that simple majority voting logic circuits, when employed in the subject environment, provide an easily realized mechanism for error correction and error detection. This results in an extremely fault tolerant information system.
摘要翻译：具有改进的纠错和检测特性的容错电路以协作的方式利用了两种不同形式的信息冗余：模块冗余和奇偶校验位冗余。特别地，显示出简单多数表决逻辑电路在被摄体环境中使用时提供了一种容易实现的纠错和错误检测机制。这导致极其容错的信息系统。

4. 发明授权

US4228520A High speed multiplier using carry-save/propagate pipeline with sparse carries 失效
标题翻译：高速乘法器采用携带保存/传播管道与稀疏携带
公开(公告)号：US4228520A
公开(公告)日：1980-10-14
申请号：US36198
申请日：1979-05-04
申请人： Robert C. Letteney , Samuel R. Levine , David T. Shen , Arnold Weinberger
发明人： Robert C. Letteney , Samuel R. Levine , David T. Shen , Arnold Weinberger
IPC分类号： G06F7/505 , G06F7/483 , G06F7/52 , G06F7/53 , G06F7/533 , G06F7/50
CPC分类号： G06F7/5334
摘要： A high speed multiply apparatus minimizes latch requirements and I/O pin requirement between chips by a new configuration which iteratively adds four multiples of a multiplicand in a stage of 4-2 carry save adders which then feed four-bit parallel adders each having four sum outputs and a carry output from the highest order bit position. Only the sum outputs are latched and then fed to a carry propagate adder on each iteration for addition to the previous partial products. Only the single carry output from each of the 4-bit parallel adders needs to be latched and then fed to another 4-bit parallel adder.
摘要翻译：高速乘法装置通过新的配置最小化锁存器要求和芯片之间的I / O引脚要求，该新配置在4-2级中迭代地添加被乘数的四个倍数，然后提供四位并行加法器，每个加法器具有四个和输出和最高位位置的进位输出。只有和输出被锁存，然后在每个迭代上馈送到进位传播加法器，以添加到先前的部分乘积。只需要从每个4位并行加法器的单个进位输出锁存，然后馈送到另一个4位并行加法器。

5. 发明授权

US4157590A Programmable logic array adder 失效
标题翻译：可编程逻辑阵列加法器
公开(公告)号：US4157590A
公开(公告)日：1979-06-05
申请号：US866689
申请日：1978-01-03
申请人： Donald G. Grice , David F. Johnson , Arnold Weinberger
发明人： Donald G. Grice , David F. Johnson , Arnold Weinberger
IPC分类号： G06F7/50 , G06F7/505 , G06F7/508
CPC分类号： G06F7/5057
摘要： This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits A.sub.i, B.sub.i of two n digit binary numbers A.sub.0, A.sub.1....A.sub.n-1 and B.sub.0, B.sub.1....B.sub.n-1 plus a carry C.sub.in. The decoders generate an output signal called a min term on a different line for each of the four possible combinations A.sub.i B.sub.i, A.sub.i B.sub.i, A.sub.i B.sub.i and A.sub.i B.sub.i of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product termsf.sub.p =f.sub.0 (A.sub.0,B.sub.0) f.sub.1 (A.sub.1,B.sub.1)....f.sub.n-1 (A.sub.n-1, B.sub.n-1) f.sub.n (C.sub.in)The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms f.sub.p. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an AND function to generate a sum bit S.sub.i that is an AND of two functions supplied by the OR array to the inputs of the latches to generate a sum S.sub.0, S.sub.1....S.sub.n-1 plus a carry C.sub.out for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an AND function.
摘要翻译：本说明书公开了一种实现在可编程逻辑阵列（PLA）中的多位二进制加法器。这里使用的特定可编程逻辑阵列具有单独的两位解码器，用于接收每个类似的两个n位二进制数A0，A1 ...的数字A 1，B 1，A 1和B 0，B 1 .... B n- 1加一个进位Cin。解码器为每对的真和补的四个可能组合AiBi，AiBi，AiBi和AiBi中的每一个生成称为最小项的输出信号。来自解码器的最小项被馈送到称为产品项发生器或AND阵列的阵列，其产生乘积项FP = F0（A0，B0）f1（A1，B1）... fn-1（An-1，Bn -1）fn（Cin）将产品条款馈送到称为产品项生成器或OR数组的和的第二个数组，其与产品项fp相加。一系列锁存器是构成解放军的逻辑元件的序列。这些锁存器各自执行AND功能，以产生和位Si，它是OR阵列提供给两个功能的AND的锁存器的输入，以产生一个和S0，S1 ....Sn-1加一个进位Cout，解放军输出的加法器。该加法器针对具有执行AND功能的锁存器的PLA进行了优化。

6. 发明授权

US4463439A Sum and carry outputs with shared subfunctions 失效
标题翻译：求和并携带具有共享子功能的输出
公开(公告)号：US4463439A
公开(公告)日：1984-07-31
申请号：US379371
申请日：1982-05-17
申请人： Arnold Weinberger
发明人： Arnold Weinberger
IPC分类号： G06F7/505 , G06F7/50 , G06F7/52
CPC分类号： G06F7/5312 , G06F7/502 , G06F7/509 , G06F2207/386
摘要： Full adder stages in this adder are made up of two half adder stages that will produce either the true or complement of the sum as a bundle of subfunction signals that can be shared between the sum and carry outputs of the full adder stage. The half adder stages come in a variety of forms to accommodate both true, both complement or one true and one complement input combinations to the stage.
摘要翻译：该加法器中的全加器级由两个半加法器级构成，它们将产生和的真或补，作为可以在全加器级的和和进位输出之间共享的子功能信号束。半加法器阶段具有各种形式，以适应真实，补充或一个真实和一个补码输入组合到阶段。

7. 发明授权

US4118786A Integrated binary-BCD look-ahead adder 失效
标题翻译：集成二进制BCD预先加法器
公开(公告)号：US4118786A
公开(公告)日：1978-10-03
申请号：US758378
申请日：1977-01-10
申请人： Samuel R. Levine , Shanker Singh , Arnold Weinberger
发明人： Samuel R. Levine , Shanker Singh , Arnold Weinberger
IPC分类号： G06F7/493 , G06F7/494 , G06F7/50 , G06F7/508
CPC分类号： G06F7/494 , G06F7/508 , G06F2207/3844 , G06F2207/4921
摘要： An improved system for adding two numbers together. The numbers may be expressed either in binary form or in binary coded decimal form (wherein each decimal digit is represented by its equivalent four binary bits). By taking advantage of "don't care" decimal input conditions, a minimal implementation of a carry look-ahead adder which can operate upon both types of numbers is obtained.
摘要翻译：一个改进的系统，将两个数字加在一起。数字可以以二进制形式或二进制编码十进制形式表示（其中每个十进制数字由其等效的四个二进制位表示）。通过利用“无关”十进制输入条件，可以获得可以对两种类型的数字进行操作的进位预读加法器的最小实现。

8. 发明授权

US4087811A Threshold decoder 失效
标题翻译：阈值解码器
公开(公告)号：US4087811A
公开(公告)日：1978-05-02
申请号：US661191
申请日：1976-02-25
申请人： Arnold Weinberger
发明人： Arnold Weinberger
IPC分类号： H03M7/04 , G06F7/76 , G06F12/04 , H03M7/00 , H03M7/08 , G06F5/00
CPC分类号： G06F7/764 , G06F12/04 , H03M7/001
摘要： Disclosed is a decoder which receives a number of coded binary-weighted input signals and which provides, on a plurality of output signal lines, a threshold related to the coded value of the input signals. The threshold is defined at the output as a consecutive sequence of output signal lines having a binary 0 value on one side of the threshold, and a consecutive sequence of output signals on the other side of the threshold having a binary value of 1. In one embodiment, a single level of binary logic receives n input signals and produces a threshold on m = 2.sup.n -1 output signal lines. A second embodiment receives n input signals which are divided into groups of signals, each group of which is applied to an intermediate threshold generator, the outputs of which are combined in a final level to provide m output signals. A further embodiment of the threshold decoder receives two groups of input signals which are combined in a first level of intermediate threshold generators, the outputs of which are then combined in a final stage which may produce more than one threshold on the output signal lines. Another further embodiment of the threshold decoder discloses a plurality of groups of input signal lines, combined in a plurality of intermediate threshold generators, the outputs of which are combined in a final level of logic to produce, selectively, a like plurality of thresholds on the output signal lines.
摘要翻译：公开了一种解码器，其接收多个编码的二进制加权输入信号，并且在多个输出信号线上提供与输入信号的编码值相关的阈值。该阈值在输出端被定义为在阈值的一侧具有二进制0值的输出信号线的连续序列，并且阈值另一侧的输出信号的连续序列具有二进制值1.在一个实施例中，单级二进制逻辑接收n个输入信号并在m = 2n-1个输出信号线上产生阈值。第二实施例接收被分成信号组的n个输入信号，每组输入信号被施加到中间阈值发生器，其输出被最终组合以提供m个输出信号。阈值解码器的另一实施例接收两组输入信号，这两组输入信号被组合在第一级中间阈值发生器中，其输出在最终级中被组合，该最终级可能在输出信号线上产生多于一个的阈值。阈值解码器的另一实施例公开了多组输入信号线，组合在多个中间阈值发生器中，其输出被组合在最终逻辑水平中，以选择性地在其上产生相似的多个阈值输出信号线。

9. 发明授权

US4627017A Address range determination 失效
标题翻译：地址范围确定
公开(公告)号：US4627017A
公开(公告)日：1986-12-02
申请号：US490764
申请日：1983-05-02
申请人： Frederick T. Blount , Arnold Weinberger
发明人： Frederick T. Blount , Arnold Weinberger
IPC分类号： G06F7/02 , G06F12/14 , G06F12/00
CPC分类号： G06F12/1441 , G06F7/026
摘要： An (M plus K)-digit accessed address is checked to see if it may fall within a range of addresses g defined by the address at one end of the range plus a variable range of addresses (g). The checking is done in a single step in a comparison of the K lowest order address digits for both addresses. The K digits of the two addresses are checked against one another in two separate segments, a pointer segment and a range segment. The pointer segments of the two addresses are examined to see if any one of three relationships which would possibly place the accessed address within the range exists. The range segments of the two addresses are examined at the same time for an additional requirement to place the accessed address in the range.
摘要翻译：检查（M + K）个数位访问地址，以查看是否可能落在由范围一端的地址加上地址（g）的可变范围所定义的地址g的范围内。在两个地址的K个最低位地址数字的比较中，单步执行检查。两个地址的K个数字在两个独立的段，一个指针段和一个范围段中互相检查。检查两个地址的指针段，以查看是否有可能将访问的地址置于该范围内的三个关系中的任何一个。同时检查两个地址的范围段，以便将访问的地址放置在该范围内的附加要求。

10. 发明授权

US4348736A Programmable logic array adder 失效
标题翻译：可编程逻辑阵列加法器
公开(公告)号：US4348736A
公开(公告)日：1982-09-07
申请号：US171215
申请日：1980-07-22
申请人： Arnold Weinberger
发明人： Arnold Weinberger
IPC分类号： G06F7/50 , G06F7/505
CPC分类号： G06F7/5057
摘要： This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two-bit decoder for receiving each like order pairs of digits A.sub.i, B.sub.i of two n digit binary numbers A.sub.0, A.sub.1 . . . A.sub.n-1 and B.sub.0, B.sub.1 . . . B.sub.n-1 plus a carry C.sub.in. The decoders generate an output signal called a minterm on a different line for each of the four possible combinations A.sub.i .multidot.B.sub.i, A.sub.i .multidot.B.sub.i, A.sub.i .multidot.B.sub.i and A.sub.i .multidot.B.sub.i of the true and complement of each pair. The minterms from the decoders are fed to an array called the product term generator or AND array which generates product termsf.sub.p =f.sub.0 (A.sub.0,B.sub.0).multidot.f.sub.1 (A.sub.1,B.sub.1).multidot. . . . .multidot.f.sub.n-1 (A.sub.n-1,B.sub.n-1).multidot.f.sub.n (C.sub.in)The product terms are fed to a second array called a sums of product terms generator or OR array that sums product terms f.sub.p. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an Exclusive-OR function to generate a sum bit S.sub.i that is an Exclusive-OR of two functions supplied by the OR array to the inputs of the latches to generate a sum S.sub.0, S.sub.1 . . . S.sub.n-1 plus a carry C.sub.out for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an Exclusive-OR function and is more efficient than known adders embodied in PLAs, in which the output latches perform an AND function.
摘要翻译：本说明书公开了一种实现在可编程逻辑阵列（PLA）中的多位二进制加法器。这里使用的特定可编程逻辑阵列具有单独的两位解码器，用于接收每个类似的两个n位二进制数字A0，A1的数字Ai，Bi的对数位。。。 An-1和B0，B1。。。 Bn-1加一个carry Cin。解码器针对每对的真实和补码的四种可能的组合AixBi，AixBi，AixBi和AixBi中的每一种，在不同的线上生成被称为minterm的输出信号。来自解码器的最小值被馈送到称为产品项发生器或AND阵列的阵列，其产生乘积项fp = f0（A0，B0）xf1（A1，B1）x。。。 xfn-1（An-1，Bn-1）xfn（Cin）将产品项提供给称为产品项生成器或OR数组的和的第二数组，其与产品项fp相加。一系列锁存器是构成解放军的逻辑元件的序列。这些锁存器各执行异或运算，以产生和OR位，即由OR阵列提供的两个功能的异或运算到锁存器的输入端以产生和S0，S1。。。在PLA的输出处，加法器的Sn-1加一个进位Cout。该加法器针对具有执行异或运算功能的锁存器的PLA进行了优化，并且比PLAs中体现的已知加法器更有效，其中输出锁存器执行AND功能。

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