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1. 发明授权

US06927460B1 Method and structure for BiCMOS isolated NMOS transistor 有权
标题翻译： BiCMOS隔离NMOS晶体管的方法和结构
公开(公告)号：US06927460B1
公开(公告)日：2005-08-09
申请号：US10368253
申请日：2003-02-18
申请人： Steven M. Leibiger , Ronald B. Hulfachor , Michael Harley-Stead , Daniel J. Hahn
发明人： Steven M. Leibiger , Ronald B. Hulfachor , Michael Harley-Stead , Daniel J. Hahn
IPC分类号： H01L21/8234 , H01L21/8249 , H01L27/06 , H01L29/76 , H01L31/062 , H01L31/113 , H01L31/119 , H01L23/94
CPC分类号： H01L27/0623 , H01L21/823481 , H01L21/823493 , H01L21/8249
摘要： A structure of and a method for making an isolated NMOS transistor using standard BiCMOS processing steps and techniques. No additional masks and processing steps are needed for the isolated NMOS device relative to the standard process flow. A P-type substrate with an overlaying buried N-type layer overlaid with a buried p-type layer below a P-well is shown. An N-type region surrounds and isolates the P-well from other devices on the same wafer. N+ regions are formed in the p-well for the source and drain connections and poly or other such electrical conductors are formed on the gate, drain and source structures to make the NMOS device operational. Parasitic bipolar transistors are managed by the circuit design, current paths and biasing to ensure the parasitic bipolar transistors do not turn on.
摘要翻译：使用标准BiCMOS处理步骤和技术制造隔离NMOS晶体管的结构和方法。相对于标准工艺流程，隔离NMOS器件不需要额外的掩模和处理步骤。示出了在P阱下面覆盖有掩埋p型层的覆盖掩埋N型层的P型衬底。 N型区域围绕并隔离同一晶片上的P阱与其他器件。在源极和漏极连接的p阱中形成N +区，并且在栅极，漏极和源极结构上形成多个或其它这样的电导体，以使NMOS器件工作。寄生双极晶体管由电路设计，电流路径和偏置来管理，以确保寄生双极晶体管不导通。

2. 发明授权

US06972472B1 Quasi self-aligned single polysilicon bipolar active device with intentional emitter window undercut 失效
标题翻译：准自对准单多晶硅双极有源器件，有意发射器窗口底切
公开(公告)号：US06972472B1
公开(公告)日：2005-12-06
申请号：US10395460
申请日：2003-03-24
申请人： Steven M. Leibiger , Daniel J. Hahn , Laurence M. Szendrei
发明人： Steven M. Leibiger , Daniel J. Hahn , Laurence M. Szendrei
IPC分类号： H01L21/331 , H01L29/08 , H01L29/00
CPC分类号： H01L29/66272 , H01L29/0804
摘要： An emitter stack for a quasi-self-aligned bipolar (NPN or PNP) transistor is formed where two layers over the emitter of a silicon substrate are windowed in a manner to under cut the top layer thereby exposing the substrate material. The emitter polysilicon structure is then formed over the window and conformally extends into the undercut region thereby widening the emitter region and so reducing the distance between the edge of the emitter and the extrinsic base (the base link distance) and therefore reducing the total base resistance of the transistor.
摘要翻译：形成用于准自对准双极（NPN或PNP）晶体管的发射极叠层，其中硅衬底的发射极上的两层以下切割顶层的方式开窗，从而暴露衬底材料。然后在窗口上形成发射极多晶硅结构，并保形地延伸到底切区域，从而扩大发射极区域，从而减小发射极边缘与非本征基极之间的距离（基极距离），从而降低总基极电阻的晶体管。

3. 发明申请

US20130292771A1 METHOD AND APPARATUS FOR INTEGRATED CIRCUIT PROTECTION 有权
标题翻译：集成电路保护方法与装置
公开(公告)号：US20130292771A1
公开(公告)日：2013-11-07
申请号：US13862008
申请日：2013-04-12
申请人： Sam Zheng , Gary Sun , Steven M. Leibiger , Tyler Daigle , Julie Lynn Stultz
发明人： Sam Zheng , Gary Sun , Steven M. Leibiger , Tyler Daigle , Julie Lynn Stultz
IPC分类号： H01L27/02
CPC分类号： H01L27/0266 , H01L27/0255
摘要： In certain examples an integrated circuit protection circuit can include a circuit module, and an isolation device. The isolation device can be configured to couple a ground node of the circuit module to a power ground in an on state, and to isolate the ground node of the circuit module from the power ground in an off state, wherein the isolation module is configured to enter the off state when the IC receives a negative input voltage.
摘要翻译：在某些示例中，集成电路保护电路可以包括电路模块和隔离装置。隔离装置可以被配置为将电路模块的接地节点耦合到处于导通状态的电源地，并将电路模块的接地节点与电源地隔离在关闭状态，其中隔离模块被配置为当IC接收到负输入电压时，进入关闭状态。

4. 发明授权

US5466960A BiCMOS device having self-aligned well tap and method of fabrication 失效
标题翻译：具有自对准阱的BiCMOS器件及其制造方法
公开(公告)号：US5466960A
公开(公告)日：1995-11-14
申请号：US753272
申请日：1991-08-20
申请人： Vida Ilderem , Steven M. Leibiger
发明人： Vida Ilderem , Steven M. Leibiger
IPC分类号： H01L27/06 , H01L21/285 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8249 , H01L23/522 , H01L27/092 , H01L27/02
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/76889 , H01L21/8249 , H01L23/5222 , H01L29/665 , H01L2924/0002
摘要： A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits higher packing density, and lowers buried layer-to-substrate capacitance.
摘要翻译：提供了使用单个多晶硅工艺和硅化物层形成的场效应器件的阱抽头。与阱接触的多晶硅层以与阱相同的方式掺杂，但与源极或漏极相反地掺杂。硅化物层形成在源极或漏极的上表面和侧壁表面，阱阱阱和用于场效应器件的栅极触点。硅化物层从侧壁硅化物穿过晶体管的上表面延伸到晶体管栅极的侧壁氧化物。该结构使得可以消除先前设备中使用的横向间隔开的分离井口。消除横向间隔的阱抽头允许更高的堆积密度，并降低掩埋层对衬底的电容。

5. 发明授权

US06700474B1 High value polysilicon resistor 失效
标题翻译：高价值多晶硅电阻
公开(公告)号：US06700474B1
公开(公告)日：2004-03-02
申请号：US10225636
申请日：2002-08-22
申请人： Steven M. Leibiger
发明人： Steven M. Leibiger
IPC分类号： H01C1012
CPC分类号： H01L28/20 , H01L27/0629 , H01L27/0802
摘要： A resistor structure is disclosed that is constructed out of two layers of polysilicon. The intrinsic device is made using the top layer which is either a dedicated deposition, or formed as part of an existing process step such as a base epi growth in a BiCMOS flow. This poly layer can be made with a relatively high (greater than 2000 ohms per square) sheet resistance by appropriate scaling of the implant dose or by insitu doping methods. The resistor ends are formed by the addition of a bottom poly layer in a self aligned manner with a deposition which may already be part of the process sequence. The end result is that the intrinsic resistor body is formed of a single poly layer, while the ends are created out of two layers. These ends are thick enough so that standard silicide and contact etch processing may be added to the structure without special care. In addition, dedicated or already available implants may be incorporated into the resistor ends to ensure ohmic contacts from polysilicon to the silicide or the contact metal are achieved. These steps can produce an easily fabricated resistor structure with consistent, low resistance, ohmic end contacts, and intrinsic resistance of greater than 2000 ohms per square.
摘要翻译：公开了由两层多晶硅构成的电阻器结构。本征器件是使用作为专用沉积的顶层制成的，或者形成为现有工艺步骤的一部分，例如BiCMOS流中的底部epi生长。可以通过适当缩放植入剂量或通过本征掺杂方法，以相对较高（大于2000欧姆/平方）的薄层电阻制造该多层。电阻器端通过以自对准的方式添加底部多层形成，其中沉积可能已经是处理顺序的一部分。最终结果是固有电阻体由单个多晶层形成，而端部由两层构成。这些端部足够厚，使得可以在没有特别小心的情况下将标准硅化物和接触蚀刻处理添加到结构中。此外，可以将专用或已经可用的植入物结合到电阻器端部中以确保实现从多晶硅到硅化物或接触金属的欧姆接触。这些步骤可以产生容易制造的电阻器结构，具有一致，低电阻，欧姆端触点和大于2000欧姆每平方的固有电阻。

6. 发明授权

US07018778B1 Single polisilicon emitter bipolar junction transistor processing technique using cumulative photo resist application and patterning 有权
标题翻译：单晶硅发射极双极结晶体管加工技术，采用累积光刻胶应用和图案化
公开(公告)号：US07018778B1
公开(公告)日：2006-03-28
申请号：US10395499
申请日：2003-03-24
申请人： Steven M. Leibiger , Laurence M. Szendrei , Mark A. Doyle
发明人： Steven M. Leibiger , Laurence M. Szendrei , Mark A. Doyle
IPC分类号： G03F7/26
CPC分类号： H01L29/0817 , H01L29/66242 , H01L29/7375
摘要： A process for forming a bipolar transistor where the doping implantation of the extrinsic base regions does not affect the emitter doping levels. The techniques is to not remove the photoresist layer used to define the poly emitter contact. The photoresist layer for defining the extrinsic base regions overlays the photoresist layer over the emitter poly. When the base photoresist is processed to expose the base regions the photoresist over the emitter poly remains in tact. In this arrangement the base implantation is prevented from driving through the emitter poly and affecting the doping levels in the emitter.
摘要翻译：用于形成双极晶体管的工艺，其中外部基极区域的掺杂注入不影响发射极掺杂水平。这些技术是不去除用于限定多晶硅发射极触点的光致抗蚀剂层。用于限定非本征基区的光致抗蚀剂层覆盖发光体多晶硅上的光致抗蚀剂层。当基底光致抗蚀剂被处理以露出基底区域时，发射体聚合物上的光致抗蚀剂保持在触感中。在这种布置中，防止基极注入驱动穿过发射极多晶并影响发射极中的掺杂水平。

7. 发明授权

US5079182A BiCMOS device having self-aligned well tap and method of fabrication 失效
标题翻译：具有自对准井口的BICMOS设备和制造方法
公开(公告)号：US5079182A
公开(公告)日：1992-01-07
申请号：US503345
申请日：1990-04-02
申请人： Vida Ilderem , Steven M. Leibiger
发明人： Vida Ilderem , Steven M. Leibiger
IPC分类号： H01L27/06 , H01L21/285 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8249 , H01L23/522 , H01L27/092
CPC分类号： H01L21/76897 , H01L21/28525 , H01L21/76889 , H01L21/8249 , H01L23/5222 , H01L29/665 , H01L2924/0002
摘要： A well tap for a field effect device formed using a single polysilicon process and a silicide layer is provided. The polysilicon layer which makes contact to the well is doped the same way as the well but is doped opposite of the source or drain. The silicide layer is formed on the upper and sidewall surfaces of the source or drain, well tap, and gate contacts for a field effect device. The silicide layer extends from the sidewall silicide across the upper surface of the transistors and up to the sidewall oxide of the transistor gates. The structure makes it possible to eliminate laterally-spaced separate well taps used in previous devices. Elimination of the laterally-spaced well taps permits hgher packing density, and lowers buried layer-to-substrate capacitance.

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