专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07705389B2 Thickened sidewall dielectric for memory cell 有权
标题翻译：用于存储单元的增厚的侧壁电介质
公开(公告)号：US07705389B2
公开(公告)日：2010-04-27
申请号：US11847183
申请日：2007-08-29
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

2. 发明授权

US08643082B2 Thickened sidewall dielectric for memory cell 有权
标题翻译：用于存储单元的增厚的侧壁电介质
公开(公告)号：US08643082B2
公开(公告)日：2014-02-04
申请号：US13276600
申请日：2011-10-19
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

3. 发明申请

US20090057744A1 THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL 有权
标题翻译：用于记忆体的厚度小的电介质
公开(公告)号：US20090057744A1
公开(公告)日：2009-03-05
申请号：US11847183
申请日：2007-08-29
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

4. 发明申请

US20120032252A1 THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL 有权
标题翻译：用于记忆体的厚度小的电介质
公开(公告)号：US20120032252A1
公开(公告)日：2012-02-09
申请号：US13276600
申请日：2011-10-19
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

5. 发明授权

US08058140B2 Thickened sidewall dielectric for memory cell 有权
标题翻译：用于存储单元的增厚的侧壁电介质
公开(公告)号：US08058140B2
公开(公告)日：2011-11-15
申请号：US12757869
申请日：2010-04-09
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L21/76
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

6. 发明申请

US20100197131A1 THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL 有权
标题翻译：用于记忆体的厚度小的电介质
公开(公告)号：US20100197131A1
公开(公告)日：2010-08-05
申请号：US12757869
申请日：2010-04-09
申请人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
发明人： Ron Weimer , Kyu Min , Tom Graettinger , Nirmal Ramaswamy
IPC分类号： H01L21/302
CPC分类号： H01L27/11568 , H01L27/115
摘要： Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
摘要翻译：公开了诸如涉及具有改进的电荷保持特性的存储单元装置的方法和装置。在一个或多个实施例中，提供具有由相邻沟槽的侧壁限定的有源区的存储单元。一层电介质材料被覆盖在该存储单元上，并被蚀刻以在有源区的侧壁上形成间隔物。在有源区上形成电介质材料，在有源区上方的电介质材料上形成电荷捕捉结构，在电荷俘获结构上方形成一个控制栅极。在一些实施例中，电荷捕获结构包括纳米点。在一些实施例中，间隔物的宽度在分离电荷俘获材料的电介质材料的厚度和活性区域的上表面之间的约130％至约170％之间。

7. 发明授权

US06707090B2 DRAM cell constructions 有权
标题翻译： DRAM单元结构
公开(公告)号：US06707090B2
公开(公告)日：2004-03-16
申请号：US10393696
申请日：2003-03-20
申请人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
发明人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
IPC分类号： H01L27108
CPC分类号： H01L27/10858 , H01L27/1082 , H01L27/1203 , H01L28/91 , Y10S257/906
摘要： The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate containing a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further contains a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.
摘要翻译：本发明包括形成DRAM单元的方法。第一衬底被形成为包括通过绝缘材料彼此分离的第一DRAM子结构。包含单晶材料的第二半导体衬底被结合到第一衬底。在接合之后，第二DRAM子结构形成为与第一DRAM子结构电连接。本发明还包括具有电容器结构的半导体结构以及限定为包围电容器结构的第一衬底。半导体结构还包含结合到第一衬底和电容器结构上的单晶硅衬底。另外，半导体结构包括在单晶硅衬底上的晶体管栅极，并且与电容器结构可操作地连接以限定DRAM单元。

8. 发明授权

US06458714B1 Method of selective oxidation in semiconductor manufacture 有权
标题翻译：半导体制造中选择性氧化的方法
公开(公告)号：US06458714B1
公开(公告)日：2002-10-01
申请号：US09721839
申请日：2000-11-22
申请人： Don Carl Powell , Ron Weimer , Lyle Breiner , Howard Rhodes , Jeff McKee , David Kubista
发明人： Don Carl Powell , Ron Weimer , Lyle Breiner , Howard Rhodes , Jeff McKee , David Kubista
IPC分类号： H01L21311
CPC分类号： H01L21/3003 , H01L21/32105
摘要： Disclosed is a method of selective oxidation of components of a semiconductor transistor containing silicon in the presence of high conductivity metal or metal alloys. A high temperature annealing step allows hydrogen gas to permeate the surface of a metal or metal alloy and creates a hydrogen-terminated passivation layer that surrounds the metallic layer. This passivating layer protects the underlying metal or metal alloy from oxidation by oxygen or water and reduces any oxidized metal present back into the constituent metal or metal alloy. In a subsequent wet oxidation step the source and drain regions of a semiconductor transistor gate electrode are reoxidized without oxidation of the passivated metal or metal alloy. The process does not consume the metal or metal alloy layer, insures that the overall gate electrode resistance remains low, and preserves the desirable characteristics of the gate electrode that insure a quality component with superior longevity.
摘要翻译：公开了一种在高导电性金属或金属合金存在下选择性氧化含有硅的半导体晶体管的部件的方法。高温退火步骤允许氢气渗透到金属或金属合金的表面，并产生围绕金属层的氢封端钝化层。该钝化层保护下面的金属或金属合金免受氧气或水的氧化，并减少存在于组成金属或金属合金中的任何氧化金属。在随后的湿式氧化步骤中，半导体晶体管栅极的源极和漏极区域被再氧化，而不会钝化钝化的金属或金属合金。该过程不消耗金属或金属合金层，确保整个栅电极电阻保持较低，并且保持了确保具有优异寿命的质量分量的栅电极的期望特性。

9. 发明授权

US06429070B1 DRAM cell constructions, and methods of forming DRAM cells 有权
标题翻译： DRAM单元结构以及形成DRAM单元的方法
公开(公告)号：US06429070B1
公开(公告)日：2002-08-06
申请号：US09651484
申请日：2000-08-30
申请人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
发明人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
IPC分类号： H01L218242
CPC分类号： H01L27/10858 , H01L27/1082 , H01L27/1203 , H01L28/91 , Y10S257/906
摘要： The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate including a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which includes a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.
摘要翻译：本发明包括形成DRAM单元的方法。第一衬底被形成为包括通过绝缘材料彼此分离的第一DRAM子结构。包括单晶材料的第二半导体衬底被结合到第一衬底。在接合之后，第二DRAM子结构形成为与第一DRAM子结构电连接。本发明还包括一种包括电容器结构的半导体结构和被限定为包围电容器结构的第一衬底。半导体结构还包括结合到第一衬底和电容器结构上的单晶硅衬底。另外，半导体结构包括在单晶硅衬底上的晶体管栅极，并且与电容器结构可操作地连接以限定DRAM单元。

10. 发明授权

US06639243B2 DRAM cell constructions 有权
标题翻译： DRAM单元结构
公开(公告)号：US06639243B2
公开(公告)日：2003-10-28
申请号：US10012233
申请日：2001-12-05
申请人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
发明人： Fernando Gonzalez , Kevin L. Beaman , John T. Moore , Ron Weimer
IPC分类号： H01L27108
CPC分类号： H01L27/10858 , H01L27/1082 , H01L27/1203 , H01L28/91 , Y10S257/906
摘要： The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.
摘要翻译：本发明包括形成DRAM单元的方法。第一衬底被形成为包括通过绝缘材料彼此分离的第一DRAM子结构。具有单晶材料的第二半导体衬底被结合到第一衬底。在接合之后，第二DRAM子结构形成为与第一DRAM子结构电连接。本发明还包括具有电容器结构的半导体结构以及限定为包围电容器结构的第一衬底。半导体结构还包括结合到第一衬底和电容器结构上的单晶硅衬底。另外，半导体结构包括在单晶硅衬底上的晶体管栅极，并且与电容器结构可操作地连接以限定DRAM单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式