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1. 发明申请

US20100073388A1 UNIFIED MEMORY ARCHITECTURE AND DISPLAY CONTROLLER TO PREVENT DATA FEED UNDER-RUN 有权
标题翻译：统一的存储器架构和显示控制器，用于防止数据馈送不足
公开(公告)号：US20100073388A1
公开(公告)日：2010-03-25
申请号：US12596235
申请日：2007-04-26
申请人： Roman Mostinski , Mikhail Bourgart , Edward Vaiberman
发明人： Roman Mostinski , Mikhail Bourgart , Edward Vaiberman
IPC分类号： G09G5/36 , G09G5/00
CPC分类号： G09G5/363 , G09G5/397 , G09G2340/02 , G09G2360/125
摘要： A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory which receives pixel data and transmits the pixel data through a main route and a secondary route; wherein pixel data is transmitted through the main route and is processed for delivery to the display in a predetermined manner; characterised in that the secondary route comprises a memory for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time; further characterised in that the display controller includes a detector for identifying a data feed latency event and in response there to switching the transmission of the pixel data to the secondary route and processing the pixel data through secondary route for delivery to the display such that when a data feed latency event occurs the stored two-dimensional section of the pixel data from the secondary route is displayed on the display.
摘要翻译：一种显示控制器，用于控制发生数据馈送等待时间波动的同步显示中的数据，所述显示控制器包括接收像素数据并通过主路线和次路径发送像素数据的输入存储器; 其中像素数据通过主路由发送并被处理以预定方式传送到显示器; 其特征在于，所述次路径包括用于存储所述像素数据的二维部分的存储器，所述二维部分至少部分地对应于当时通过所述主路线传输的像素数据; 其特征还在于，所述显示控制器包括用于识别数据馈送等待时间事件的检测器，并且响应于将所述像素数据的传输切换到所述辅助路由并通过辅助路由处理所述像素数据以传送到所述显示器，使得当数据馈送等待时间事件发生在二维路由的像素数据的存储二维部分显示在显示器上。

2. 发明授权

US08462141B2 Unified memory architecture and display controller to prevent data feed under-run 有权
标题翻译：统一的内存架构和显示控制器，防止数据馈送不足
公开(公告)号：US08462141B2
公开(公告)日：2013-06-11
申请号：US12596235
申请日：2007-04-26
申请人： Roman Mostinski , Mikhail Bourgart , Edward Vaiberman
发明人： Roman Mostinski , Mikhail Bourgart , Edward Vaiberman
IPC分类号： G06F3/038 , G06F15/16 , G09G5/36
CPC分类号： G09G5/363 , G09G5/397 , G09G2340/02 , G09G2360/125
摘要： A display controller for controlling data in an isochronous display where fluctuation of data feed latency occurs, the display controller including an input memory which receives pixel data and transmits the pixel data through a main route and a secondary route; wherein pixel data is transmitted through the main route and is processed for delivery to the display in a predetermined manner; characterized in that the secondary route comprises a memory for storing a two-dimensional section of the pixel data that corresponds at least in part to the pixel data being transmitted through the main route at that time; further characterized in that the display controller includes a detector for identifying a data feed latency event and in response there to switching the transmission of the pixel data to the secondary route and processing the pixel data through secondary route for delivery to the display such that when a data feed latency event occurs the stored two-dimensional section of the pixel data from the secondary route is displayed on the display.
摘要翻译：一种显示控制器，用于控制发生数据馈送等待时间波动的同步显示中的数据，所述显示控制器包括接收像素数据并通过主路线和次路径发送像素数据的输入存储器; 其中像素数据通过主路由发送并被处理以预定方式传送到显示器; 其特征在于，所述次路径包括用于存储所述像素数据的二维部分的存储器，所述二维部分至少部分地对应于当时通过所述主路线传输的像素数据; 其特征还在于，所述显示控制器包括用于识别数据馈送等待时间事件的检测器，并且响应于将所述像素数据的传输切换到所述辅助路由并通过辅助路由处理所述像素数据以传送到所述显示器，使得当数据馈送等待时间事件发生在二维路由的像素数据的存储二维部分显示在显示器上。

3. 发明授权

US07969181B1 Device and method for adjusting an impedance of an output driver of an integrated circuit 有权
标题翻译：用于调整集成电路的输出驱动器的阻抗的装置和方法
公开(公告)号：US07969181B1
公开(公告)日：2011-06-28
申请号：US12025030
申请日：2008-02-03
申请人： Yefim Fefer , Mikhail Bourgart , Sergey Sofer
发明人： Yefim Fefer , Mikhail Bourgart , Sergey Sofer
IPC分类号： H03K17/16 , H03K19/0185
CPC分类号： H03K19/017545 , H03K19/0005
摘要： A device and method for adjusting an impedance of an output driver of an integrated circuit; the method includes: (i) receiving, by the output driver, a first square wave signal that should be driven by the output driver to provide a second signal; (ii) monitoring, by a monitoring circuit included in the integrated circuit, the second signal during an output driver transient period resulting from a first square wave signal transient to provide a monitoring result; (iii) determining whether to adjust the impedance of the output driver in response to the monitoring result; and (iv) adjusting the impedance of the output driver in response to the determination.
摘要翻译：一种用于调整集成电路的输出驱动器的阻抗的装置和方法; 该方法包括：（i）由输出驱动器接收应由输出驱动器驱动以提供第二信号的第一方波信号; （ii）由包括在集成电路中的监视电路在由第一方波信号瞬态产生的输出驱动器瞬态周期期间监视第二信号以提供监视结果; （iii）响应监视结果确定是否调整输出驱动器的阻抗; 以及（iv）响应于所述确定来调整所述输出驱动器的阻抗。

4. 发明授权

US08368383B2 Method for testing a variable digital delay line and a device having variable digital delay line testing capabilities 有权
标题翻译：用于测试可变数字延迟线的方法和具有可变数字延迟线测试能力的器件
公开(公告)号：US08368383B2
公开(公告)日：2013-02-05
申请号：US12522034
申请日：2007-01-05
申请人： Yefim-Haim Fefer , Mikhail Bourgart , Segey Sofer , Yoav Weizman
发明人： Yefim-Haim Fefer , Mikhail Bourgart , Segey Sofer , Yoav Weizman
IPC分类号： H03L7/06 , H03K3/00 , G01R31/28
CPC分类号： G01R31/3016 , G01R31/2882
摘要： A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.
摘要翻译：一种用于测试包括多个抽头的可变数字延迟线的装置和方法。该方法包括向可变数字延迟线提供输入信号，并针对可变数字延迟线的测试抽头组中的每个抽头找出可变延迟单元配置，其提供最接近所引入的延迟的延迟由水龙头其中可变数字延迟线和可变延迟单元属于同一集成电路。

5. 发明申请

US20100072979A1 METHOD FOR TESTING A VARIABLE DIGITAL DELAY LINE AND A DEVICE HAVING VARIABLE DIGITAL DELAY LINE TESTING CAPABILITIES 有权
标题翻译：用于测试可变数字延迟线的方法和具有可变数字延迟线测试能力的设备
公开(公告)号：US20100072979A1
公开(公告)日：2010-03-25
申请号：US12522034
申请日：2007-01-05
申请人： Yefim-Haim Fefer , Mikhail Bourgart , Segey Sofer , Yoav Weizman
发明人： Yefim-Haim Fefer , Mikhail Bourgart , Segey Sofer , Yoav Weizman
IPC分类号： G01R25/00
CPC分类号： G01R31/3016 , G01R31/2882
摘要： A device and a method for testing a variable digital delay line that includes multiple taps. The method includes providing, an input signal to the variable digital delay line and finding, for each tap out of a group of tested taps of the variable digital delay line, a variable delay unit configuration that provides a delay that is closest to a delay introduced by the tap; wherein the variable digital delay line and the variable delay unit belong to the same integrated circuit.
摘要翻译：一种用于测试包括多个抽头的可变数字延迟线的装置和方法。该方法包括向可变数字延迟线提供输入信号，并针对可变数字延迟线的测试抽头组中的每个抽头找出可变延迟单元配置，其提供最接近所引入的延迟的延迟由水龙头其中可变数字延迟线和可变延迟单元属于同一集成电路。

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