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1. 发明授权

US06427896B1 Safety device for pneumatic nailers 有权
标题翻译：气动钉枪安全装置
公开(公告)号：US06427896B1
公开(公告)日：2002-08-06
申请号：US10055190
申请日：2002-01-25
申请人： Roman Ho , An-Chi Liu
发明人： Roman Ho , An-Chi Liu
IPC分类号： B25C104
CPC分类号： B25C1/008
摘要： A safety device for a pneumatic nailer includes a push rod which has a connection end extending through an adjusting member and a pivotal member which is mounted by the adjusting member. The adjusting member is rotatable relative to the pivotal member which is connected to a connection plate. The hole for the threaded rod of the pivotal member has tow straight insides matched with two plain surfaces on the threaded rod. Only one groove is required in the adjusting member to receive a clamp whose two legs contact two notches in the pivotal member.
摘要翻译：一种用于气动钉枪的安全装置，包括：推杆，其具有延伸穿过调节构件的连接端和由调节构件安装的枢转构件。调节构件可相对于连接到连接板的枢转构件旋转。枢转构件的螺纹杆的孔具有与螺纹杆上的两个平坦表面匹配的丝线内侧。在调节构件中仅需要一个凹槽来接收两个腿接触枢转构件中的两个凹口的夹具。

2. 发明授权

US08350334B2 Stress film forming method and stress film structure 有权
标题翻译：应力膜成型方法和应力膜结构
公开(公告)号：US08350334B2
公开(公告)日：2013-01-08
申请号：US13158541
申请日：2011-06-13
申请人： Chun-Min Wang , An-Chi Liu , Hsin-Hsing Chen , Chih-Chun Wang
发明人： Chun-Min Wang , An-Chi Liu , Hsin-Hsing Chen , Chih-Chun Wang
IPC分类号： H01L21/70
CPC分类号： H01L21/823807 , H01L21/76828 , H01L21/76832 , H01L21/823864
摘要： A stress film forming method is used in a fabrication process of a semiconductor device. Firstly, a substrate is provided, wherein a first-polarity-channel MOSFET and a second-polarity-channel MOSFET are formed on the substrate. Then, at least one deposition-curing cycle process is performed to form a cured stress film over the first-polarity-channel MOSFET and the second-polarity-channel MOSFET. Afterwards, an additional deposition process is performed form a non-cured stress film on the cured stress film, wherein the cured stress film and the non-cured stress film are collectively formed as a seamless stress film.
摘要翻译：在半导体器件的制造工艺中使用应力膜形成方法。首先，提供衬底，其中在衬底上形成第一极性沟道MOSFET和第二极性沟道MOSFET。然后，进行至少一次沉积 - 固化循环过程，以在第一极 - 沟道MOSFET和第二极 - 沟道MOSFET上形成固化的应力膜。此后，在固化的应力膜上进行非固化应力膜的附加沉积工艺，其中固化的应力膜和未固化的应力膜共同形成为无缝应力膜。

3. 发明申请

US20110053371A1 SEMICONDUCTOR PROCESS 有权
标题翻译：半导体工艺
公开(公告)号：US20110053371A1
公开(公告)日：2011-03-03
申请号：US12547780
申请日：2009-08-26
申请人： An-Chi Liu , Chih-Chien Huang , Tien-Cheng Lan
发明人： An-Chi Liu , Chih-Chien Huang , Tien-Cheng Lan
IPC分类号： H01L21/768
CPC分类号： H01L21/76811 , H01L21/02063 , H01L21/3105 , H01L21/31058 , H01L21/76814 , H01L21/76816
摘要： A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein.
摘要翻译：提供半导体制造工艺。首先，提供衬底，其上依次形成图案化导电层，电介质层和图案化的金属硬掩模层。此后，去除介电层的一部分以形成暴露图案化导电层的镶嵌开口。之后，将电介质层加热至200℃以上。此后，对镶嵌开口进行等离子体处理，其中用于产生等离子体的气体包括氢气和惰性气体。之后，在镶嵌开口中形成导电层以填充其中。

4. 发明申请

US20100260992A1 MULTI CAP LAYER 审中-公开
标题翻译：多盖层
公开(公告)号：US20100260992A1
公开(公告)日：2010-10-14
申请号：US12820157
申请日：2010-06-22
申请人： Wei-Chih Chen , An-Chi Liu
发明人： Wei-Chih Chen , An-Chi Liu
IPC分类号： B32B7/02 , H01L23/48 , H01L23/52 , B32B9/00
CPC分类号： H01L21/31144 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/31608 , H01L21/76811 , H01L21/76813 , Y10T428/2495 , Y10T428/31504 , Y10T428/31663
摘要： A multi-layer structure for forming damascene interconnects includes a substrate having at least a conductive layer and a base layer a dielectric layer formed on the substrate and covering the conductive layer and the base layer, a protecting layer covering the dielectric layer and a tensile stress layer covering the protecting layer.
摘要翻译：用于形成镶嵌互连的多层结构包括至少具有导电层和基底层的衬底，该衬底形成在衬底上并覆盖导电层和基底层，覆盖电介质层的保护层和拉伸应力覆盖保护层的层。

5. 发明授权

US07670438B2 Method of removing particles from wafer 有权
标题翻译：从晶片去除颗粒的方法
公开(公告)号：US07670438B2
公开(公告)日：2010-03-02
申请号：US11866746
申请日：2007-10-03
申请人： Yi-Wei Chen , Bao-Tzeng Huang , An-Chi Liu , Chao-Ching Hsieh , Nien-Ting Ho , Kuo-Chih Lai
发明人： Yi-Wei Chen , Bao-Tzeng Huang , An-Chi Liu , Chao-Ching Hsieh , Nien-Ting Ho , Kuo-Chih Lai
IPC分类号： B08B3/04
CPC分类号： B08B3/08 , H01L21/02068 , H01L21/67051
摘要： A method of removing particles from a wafer is provided. The method is adopted after a process for removing unreactive metal of a salicide process or after a salicide process and having oxide residue remaining on a wafer or after a chemical vapor deposition (CVD) process that resulted with particles on a wafer. The method includes performing at least two cycles (stages) of intermediate rinse process. Each cycle of the intermediate rinse process includes conducting a procedure of rotating the wafer at a high speed first, and then conducting a procedure of rotating the wafer at a low speed.
摘要翻译：提供了从晶片去除颗粒的方法。在除去自对准硅化物工艺的非反应性金属或自对准硅化物工艺之后并且在晶片上残留氧化物残余物或在晶片上产生颗粒的化学气相沉积（CVD）工艺之后，采用该方法。该方法包括进行中间漂洗过程的至少两个循环（阶段）。中间漂洗过程的每个循环包括首先进行高速旋转晶片的步骤，然后进行以低速旋转晶片的步骤。

6. 发明申请

US20130277686A1 Semiconductor Structure with Metal Gate and Method of Fabricating the Same 有权
标题翻译：金属门半导体结构及其制造方法
公开(公告)号：US20130277686A1
公开(公告)日：2013-10-24
申请号：US13454036
申请日：2012-04-23
申请人： An-Chi Liu , Chun-Hsien Lin
发明人： An-Chi Liu , Chun-Hsien Lin
IPC分类号： H01L29/161 , H01L29/772
CPC分类号： H01L29/66795 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L29/785
摘要： A metal gate process comprises the steps of providing a substrate, forming a dummy gate on said substrate, forming dummy spacers on at least one of the surrounding sidewalls of said dummy gate, forming a source and a drain respectively in said substrate at both sides of said dummy gate, performing a replacement metal gate process to replace said dummy gate with a metal gate, removing said dummy spacers, and forming low-K spacers to replace said dummy spacers.
摘要翻译：金属浇口工艺包括以下步骤：提供衬底，在所述衬底上形成虚拟栅极，在所述伪栅极的至少一个周围侧壁上形成虚设间隔物，分别在所述衬底的两侧形成源极和漏极所述虚拟栅极，执行替换金属栅极工艺以用金属栅极替换所述伪栅极，去除所述虚设间隔物，以及形成低K间隔物以代替所述虚拟间隔物。

7. 发明申请

US20130200470A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130200470A1
公开(公告)日：2013-08-08
申请号：US13367382
申请日：2012-02-07
申请人： An-Chi Liu , Chun-Hsien Lin , Yu-Cheng Tung , Chien-Ting Lin , Wen-Tai Chiang , Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen
发明人： An-Chi Liu , Chun-Hsien Lin , Yu-Cheng Tung , Chien-Ting Lin , Wen-Tai Chiang , Shih-Hung Tsai , Ssu-I Fu , Ying-Tsung Chen , Chih-Wei Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7834 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A semiconductor structure and a method of fabricating the same comprising the steps of providing a substrate, forming at least one fin structure on said substrate, forming a gate covering said fin structure, forming a plurality of epitaxial structures covering said fin structures, performing a gate pullback process to reduce the critical dimension (CD) of said gate and separate said gate and said epitaxial structures, forming lightly doped drains (LDD) in said fin structures, and forming a spacer on said gate and said fin structures.
摘要翻译：一种半导体结构及其制造方法，包括以下步骤：提供衬底，在所述衬底上形成至少一个鳍结构，形成覆盖所述鳍结构的栅极，形成覆盖所述鳍结构的多个外延结构，拉回过程以减小所述栅极的临界尺寸（CD）并分离所述栅极和所述外延结构，在所述鳍结构中形成轻掺杂的漏极（LDD），以及在所述栅极和所述鳍结构上形成间隔物。

8. 发明授权

US08114773B2 Cleaning solution, cleaning method and damascene process using the same 有权
标题翻译：清洗方法，清洗方法和镶嵌工艺使用相同
公开(公告)号：US08114773B2
公开(公告)日：2012-02-14
申请号：US12830566
申请日：2010-07-06
申请人： An-Chi Liu , Tien-Cheng Lan
发明人： An-Chi Liu , Tien-Cheng Lan
IPC分类号： H01L21/44
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/265 , C11D7/3209 , C11D7/3218 , C11D7/3245 , H01L21/02063 , H01L21/31144 , H01L21/76814
摘要： A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH4F); (d) a chelating agent containing a carboxylic group; (e) triethanolamine (TEA); (f) ethylenediaminetetraacetic acid (EDTA); and (g) water for balance.
摘要翻译：提供清洁液。清洗溶液包括（a）0.01-0.1重量％的氢氟酸（HF）; （b）1-5重量％的强酸，其中强酸是无机酸; （c）0.05-0.5重量％的氟化铵（NH4F）; （d）含有羧基的螯合剂; （e）三乙醇胺（TEA）; （f）乙二胺四乙酸（EDTA）; 和（g）平衡水。

9. 发明申请

US20120009788A1 CLEANING SOLUTION, CLEANING METHOD AND DAMASCENE PROCESS USING THE SAME 有权
标题翻译：清洁溶液，清洁方法和使用该方法的丹麦方法
公开(公告)号：US20120009788A1
公开(公告)日：2012-01-12
申请号：US12830566
申请日：2010-07-06
申请人： An-Chi Liu , Tien-Cheng Lan
发明人： An-Chi Liu , Tien-Cheng Lan
IPC分类号： H01L21/768 , C11D3/02 , B08B3/08
CPC分类号： C11D11/0047 , C11D7/08 , C11D7/265 , C11D7/3209 , C11D7/3218 , C11D7/3245 , H01L21/02063 , H01L21/31144 , H01L21/76814
摘要： A cleaning solution is provided. The cleaning solution includes (a) 0.01-0.1 wt % of hydrofluoric acid (HF); (b) 1-5 wt % of a strong acid, wherein the strong acid is an inorganic acid; (c) 0.05-0.5 wt % of ammonium fluoride (NH4F); (d) a chelating agent containing a carboxylic group; (e) triethanolamine (TEA); (f) ethylenediaminetetraacetic acid (EDTA); and (g) water for balance.
摘要翻译：提供清洁液。清洗溶液包括（a）0.01-0.1重量％的氢氟酸（HF）; （b）1-5重量％的强酸，其中强酸是无机酸; （c）0.05-0.5重量％的氟化铵（NH4F）; （d）含有羧基的螯合剂; （e）三乙醇胺（TEA）; （f）乙二胺四乙酸（EDTA）; 和（g）平衡水。

10. 发明授权

US08062972B2 Semiconductor process 有权
标题翻译：半导体工艺
公开(公告)号：US08062972B2
公开(公告)日：2011-11-22
申请号：US12547780
申请日：2009-08-26
申请人： An-Chi Liu , Chih-Chien Huang , Tien-Cheng Lan
发明人： An-Chi Liu , Chih-Chien Huang , Tien-Cheng Lan
IPC分类号： H01L21/302
CPC分类号： H01L21/76811 , H01L21/02063 , H01L21/3105 , H01L21/31058 , H01L21/76814 , H01L21/76816
摘要： A semiconductor manufacturing process is provided. First, a substrate is provided, wherein a patterned conductive layer, a dielectric layer and a patterned metal hard mask layer are sequentially formed thereon. Thereafter, a portion of the dielectric layer is removed to form a damascene opening exposing the patterned conductive layer. Afterwards, the dielectric layer is heated to above 200° C. Thereafter, a plasma treatment process is performed on the damascene opening, wherein the gases used to generate the plasma include hydrogen gas and inert gas. Afterwards, a conductive layer is formed in the damascene opening to fill therein.
摘要翻译：提供半导体制造工艺。首先，提供衬底，其上依次形成图案化导电层，电介质层和图案化金属硬掩模层。此后，去除介电层的一部分以形成暴露图案化导电层的镶嵌开口。之后，将电介质层加热至200℃以上。此后，对镶嵌开口进行等离子体处理，其中用于产生等离子体的气体包括氢气和惰性气体。之后，在镶嵌开口中形成导电层以填充其中。

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