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1. 发明授权

US4180861A Selectively operable mask generator 失效
标题翻译：选择性操作的面罩发生器
公开(公告)号：US4180861A
公开(公告)日：1979-12-25
申请号：US892064
申请日：1978-03-31
申请人： Rolfe D. Armstrong , Charles R. Lang, Jr.
发明人： Rolfe D. Armstrong , Charles R. Lang, Jr.
IPC分类号： G06F7/76 , G06F7/00
CPC分类号： G06F7/764
摘要： A mask generator for use in a digital computer receives input signals defining the beginning and the end addresses of the inhibiting bits of the mask. The mask generator includes decoder circuits for receiving the input signals and a look-ahead carry circuit whose output signals represent the mask.
摘要翻译：用于数字计算机的掩模发生器接收定义掩模的禁止位的开始和结束地址的输入信号。掩模发生器包括用于接收输入信号的解码器电路和其输出信号表示掩模的前视传送电路。

2. 发明授权

US4291407A Parity prediction circuitry for a multifunction register 失效
标题翻译：多功能寄存器的奇偶校验预测电路
公开(公告)号：US4291407A
公开(公告)日：1981-09-22
申请号：US74036
申请日：1979-09-10
申请人： Rolfe D. Armstrong
发明人： Rolfe D. Armstrong
IPC分类号： G06F11/10
CPC分类号： G06F11/10
摘要： Parity prediction circuitry for use with a multifunction register. The parity prediction circuitry includes a parity prediction circuit associated with each function of the register. A selecting multiplexer selects the parity prediction circuit that will provide a predicted parity bit at the output of the parity prediction circuitry, with the selection controlled by the same control signals that select the function of the register. The parity prediction circuits associated with COUNT UP and COUNT DOWN functions also include a multiplexer, with this multiplexer having data inputs connected in a predetermined fashion to signals having a value of either logic level "1" or logic level "0". This multiplexer has control inputs connected to the data outputs of the register and has a data output selected by the control inputs in order to provide a signal indicating whether the predicted parity is to change from the previous predicted parity.
摘要翻译：用于多功能寄存器的奇偶校验预测电路。奇偶校验预测电路包括与寄存器的每个功能相关联的奇偶校验预测电路。选择多路复用器选择将在奇偶校验预测电路的输出处提供预测奇偶校验位的奇偶校验预测电路，其选择由选择寄存器功能的相同控制信号控制。与COUNT UP和COUNT DOWN功能相关联的奇偶校验预测电路还包括多路复用器，该多路复用器具有以预定方式连接到具有逻辑电平“1”或逻辑电平“0”的值的信号的数据输入。该多路复用器具有连接到寄存器的数据输出的控制输入，并且具有由控制输入选择的数据输出，以便提供指示预测奇偶校验是否从先前预测奇偶校验变化的信号。

3. 发明授权

US4160290A One-bit multifunction arithmetic and logic circuit 失效
标题翻译：一位多功能算术和逻辑电路
公开(公告)号：US4160290A
公开(公告)日：1979-07-03
申请号：US894795
申请日：1978-04-10
申请人： Rolfe D. Armstrong
发明人： Rolfe D. Armstrong
IPC分类号： G06F7/00 , G06F7/50 , G06F7/501 , G06F7/575 , H03K19/08
CPC分类号： G06F7/501 , G06F7/575 , G06F2207/3896
摘要： A one bit multifunction arithmetic and logic circuit is implemented with a pair of inverters, four two input NOR gates, three two-input OR/NOR gates, and two three-input NOR gates. Each of the inverters has four wire OR-able outputs, two of which are inverting and two of which are non-inverting. One input of each of the four two-input NOR gates is coupled to a respective one of four control inputs of the arithmetic and logic circuit; the other input thereof is coupled to respective ones of four wire ORed combinations of the outputs of the first and second inverters. Various outputs of the first, second, third, and fourth two-input NOR gates are wire ORed together. A first one of the three-input NOR gates is responsive to the generate signal, a carry signal, and the wired OR output of the first and second two-input NOR gates. The second three-input NOR gate is responsive to the propagate signal, a carry signal, and the "output disable" input. The first outputs of the first and second three-input NOR gates are wire ORed together to produce a first "sum" output; the second output of the first and second three-input NOR gates are wire ORed together to produce a second sum output which may be used as a wire OR-able "zero result" indicator signal.

4. 发明授权

US4751639A Virtual command rollback in a fault tolerant data processing system 失效
标题翻译：在容错数据处理系统中的虚拟命令回滚
公开(公告)号：US4751639A
公开(公告)日：1988-06-14
申请号：US748361
申请日：1985-06-24
申请人： Jon M. Corcoran , Rolfe D. Armstrong , Victor F. Cole , Chiman R. Patel
发明人： Jon M. Corcoran , Rolfe D. Armstrong , Victor F. Cole , Chiman R. Patel
IPC分类号： G06F11/14 , G06F11/16 , G06F11/18 , G06F15/16 , G06F15/177 , G06F11/08
CPC分类号： G06F11/165 , G06F11/141 , G06F11/1608
摘要： A fault tolerant data processing system includes a pair of processors for simultaneously executing commands for processing data, a memory, and a data transmission bus between the processors and the memory voer which the processors may fetch data from and write data to the memory. A comparison circuit is included between the processors for comparing the data fetched and written by the processors. A rollback module is responsive to the comparison circuit for rolling back the operation of the processors to the beginning of a presently executing command in the event of a miscomparison by the comparison circuit.
摘要翻译：容错数据处理系统包括一对处理器，用于在处理器和存储器器之间同时执行处理数据，存储器和数据传输总线的命令，处理器可以从存储器提取数据并将数据写入存储器。处理器之间包括比较电路，用于比较由处理器获取和写入的数据。回滚模块响应于比较电路，以便在比较电路错误比较的情况下将处理器的操作回滚到当前执行的命令的开始。

5. 发明授权

US4394729A Jump return stack 失效
标题翻译：跳回栈
公开(公告)号：US4394729A
公开(公告)日：1983-07-19
申请号：US197417
申请日：1980-10-16
申请人： Rolfe D. Armstrong
发明人： Rolfe D. Armstrong
IPC分类号： G06F9/26 , G06F9/22 , G06F9/34 , G06F9/38 , G06F9/42
CPC分类号： G06F9/4426
摘要： A jump return stack is provided in a data processor having a plurality of control registers including a fetch control register and an execution control register. The jump return stack comprises a memory stack, an address register, and a counter-register interposed between the memory stack and the control registers of the data processor. The counter-register is always made to store the latest entry into the memory stack, that is the top of the stack, such that the latest entry into the stack is immediately available to the control registers of the data processor thereby eliminating a memory access to the stack.
摘要翻译：在具有包括取出控制寄存器和执行控制寄存器的多个控制寄存器的数据处理器中提供跳转返回堆栈。跳转返回堆栈包括存储器堆栈，地址寄存器和插入在存储器堆栈和数据处理器的控制寄存器之间的计数器寄存器。总是将计数器寄存器存储到存储器堆栈中，这是堆栈的顶部，使得堆栈中的最新条目立即可用于数据处理器的控制寄存器，从而消除对存储器的访问堆栈。

6. 发明授权

US4315313A Diagnostic circuitry in a data processor 失效
标题翻译：数据处理器中的诊断电路
公开(公告)号：US4315313A
公开(公告)日：1982-02-09
申请号：US107735
申请日：1979-12-27
申请人： Rolfe D. Armstrong , Dennis A. Walsh
发明人： Rolfe D. Armstrong , Dennis A. Walsh
IPC分类号： G06F11/22 , G06F9/38 , G06F11/07 , G06F11/34 , G06F11/00
CPC分类号： G06F11/0772 , G06F11/0721 , G06F11/3476 , G06F11/348
摘要： Diagnostic circuitry for use with the processor of a data processing system. The diagnostic circuitry includes a control register execution log for receiving control store addresses from a control register associated with an "EXECUTE+1" stage. A log pointer addresses the log when control store addresses are written into or read from the log. Test registers connected to the log and log pointer provide control store addresses and decrementing log addresses when the contents of the log are examined. One of the test registers is also used to hold a control store address for comparison with control store addresses of executing microinstructions, and when a match occurs, to generate a SYNC signal.
摘要翻译：与数据处理系统的处理器一起使用的诊断电路。诊断电路包括用于从与“EXECUTE + 1”级相关联的控制寄存器接收控制存储地址的控制寄存器执行日志。当控制存储地址被写入日志或从日志中读取时，日志指针用于寻址日志。连接到日志和日志指针的测试寄存器在检查日志的内容时提供控制存储地址和递减的日志地址。其中一个测试寄存器也用于保存控制存储地址，以便与执行微指令的控制存储地址进行比较，当匹配发生时，产生SYNC信号。

7. 发明授权

US4177455A Electrically configurable high-low decoder 失效
标题翻译：电气可配置的高低解码器
公开(公告)号：US4177455A
公开(公告)日：1979-12-04
申请号：US867853
申请日：1978-01-09
申请人： Rolfe D. Armstrong , George B. Gillow
发明人： Rolfe D. Armstrong , George B. Gillow
IPC分类号： H03M7/00 , H03K13/243
CPC分类号： H03M7/001
摘要： An electrically configurable decoder including selectively configurable combinations of a plurality of basic decode circuits. The electrically configurable decoder includes a plurality of mode selection inputs, a plurality of address inputs, a plurality of logic level definition inputs, and a plurality of disable inputs. Various combinations of decoding functions are provided by the electrically configurable decoder in response to the mode selection inputs. A plurality of selection circuits selectively decodes various ones of the address inputs and mode selection inputs to produce signals which are applied to decode inputs and enable inputs of the basic decoder circuits. A logical "one" applied to a first one of the logic level definition inputs causes "high" and "low" voltage levels produced at the outputs of a first one of the basic decoder circuits to represent logical "ones" and "zeroes," respectively. A disable signal applied to one of the disable inputs of the electrically configurable decoder causes the outputs of the first basic decoder circuits to assume logical "zero" levels as determined by the first logic level definition input.
摘要翻译：一种电气可配置解码器，包括多个基本解码电路的可选配置的组合。电可配置解码器包括多个模式选择输入，多个地址输入，多个逻辑电平定义输入和多个禁用输入。响应于模式选择输入，电可配置解码器提供各种解码功能的组合。多个选择电路选择性地解码地址输入和模式选择输入中的各种，以产生应用于解码输入和使能基本解码器电路的输入的信号。应用于逻辑电平定义输入中的第一个逻辑电平定义输入的逻辑“1”导致在第一个基本解码器电路的输出处产生的“高”和“低”电压电平来表示逻辑“1”和“零” 分别。施加到电可配置解码器的禁用输入之一的禁用信号使第一基本解码器电路的输出呈现由第一逻辑电平定义输入确定的逻辑“零”电平。

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