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    • 1. 发明授权
    • Parity prediction circuitry for a multifunction register
    • 多功能寄存器的奇偶校验预测电路
    • US4291407A
    • 1981-09-22
    • US74036
    • 1979-09-10
    • Rolfe D. Armstrong
    • Rolfe D. Armstrong
    • G06F11/10
    • G06F11/10
    • Parity prediction circuitry for use with a multifunction register. The parity prediction circuitry includes a parity prediction circuit associated with each function of the register. A selecting multiplexer selects the parity prediction circuit that will provide a predicted parity bit at the output of the parity prediction circuitry, with the selection controlled by the same control signals that select the function of the register. The parity prediction circuits associated with COUNT UP and COUNT DOWN functions also include a multiplexer, with this multiplexer having data inputs connected in a predetermined fashion to signals having a value of either logic level "1" or logic level "0". This multiplexer has control inputs connected to the data outputs of the register and has a data output selected by the control inputs in order to provide a signal indicating whether the predicted parity is to change from the previous predicted parity.
    • 用于多功能寄存器的奇偶校验预测电路。 奇偶校验预测电路包括与寄存器的每个功能相关联的奇偶校验预测电路。 选择多路复用器选择将在奇偶校验预测电路的输出处提供预测奇偶校验位的奇偶校验预测电路,其选择由选择寄存器功能的相同控制信号控制。 与COUNT UP和COUNT DOWN功能相关联的奇偶校验预测电路还包括多路复用器,该多路复用器具有以预定方式连接到具有逻辑电平“1”或逻辑电平“0”的值的信号的数据输入。 该多路复用器具有连接到寄存器的数据输出的控制输入,并且具有由控制输入选择的数据输出,以便提供指示预测奇偶校验是否从先前预测奇偶校验变化的信号。
    • 3. 发明授权
    • One-bit multifunction arithmetic and logic circuit
    • 一位多功能算术和逻辑电路
    • US4160290A
    • 1979-07-03
    • US894795
    • 1978-04-10
    • Rolfe D. Armstrong
    • Rolfe D. Armstrong
    • G06F7/00G06F7/50G06F7/501G06F7/575H03K19/08
    • G06F7/501G06F7/575G06F2207/3896
    • A one bit multifunction arithmetic and logic circuit is implemented with a pair of inverters, four two input NOR gates, three two-input OR/NOR gates, and two three-input NOR gates. Each of the inverters has four wire OR-able outputs, two of which are inverting and two of which are non-inverting. One input of each of the four two-input NOR gates is coupled to a respective one of four control inputs of the arithmetic and logic circuit; the other input thereof is coupled to respective ones of four wire ORed combinations of the outputs of the first and second inverters. Various outputs of the first, second, third, and fourth two-input NOR gates are wire ORed together. A first one of the three-input NOR gates is responsive to the generate signal, a carry signal, and the wired OR output of the first and second two-input NOR gates. The second three-input NOR gate is responsive to the propagate signal, a carry signal, and the "output disable" input. The first outputs of the first and second three-input NOR gates are wire ORed together to produce a first "sum" output; the second output of the first and second three-input NOR gates are wire ORed together to produce a second sum output which may be used as a wire OR-able "zero result" indicator signal.
    • 5. 发明授权
    • Jump return stack
    • 跳回栈
    • US4394729A
    • 1983-07-19
    • US197417
    • 1980-10-16
    • Rolfe D. Armstrong
    • Rolfe D. Armstrong
    • G06F9/26G06F9/22G06F9/34G06F9/38G06F9/42
    • G06F9/4426
    • A jump return stack is provided in a data processor having a plurality of control registers including a fetch control register and an execution control register. The jump return stack comprises a memory stack, an address register, and a counter-register interposed between the memory stack and the control registers of the data processor. The counter-register is always made to store the latest entry into the memory stack, that is the top of the stack, such that the latest entry into the stack is immediately available to the control registers of the data processor thereby eliminating a memory access to the stack.
    • 在具有包括取出控制寄存器和执行控制寄存器的多个控制寄存器的数据处理器中提供跳转返回堆栈。 跳转返回堆栈包括存储器堆栈,地址寄存器和插入在存储器堆栈和数据处理器的控制寄存器之间的计数器寄存器。 总是将计数器寄存器存储到存储器堆栈中,这是堆栈的顶部,使得堆栈中的最新条目立即可用于数据处理器的控制寄存器,从而消除对存储器的访问 堆栈。
    • 7. 发明授权
    • Electrically configurable high-low decoder
    • 电气可配置的高低解码器
    • US4177455A
    • 1979-12-04
    • US867853
    • 1978-01-09
    • Rolfe D. ArmstrongGeorge B. Gillow
    • Rolfe D. ArmstrongGeorge B. Gillow
    • H03M7/00H03K13/243
    • H03M7/001
    • An electrically configurable decoder including selectively configurable combinations of a plurality of basic decode circuits. The electrically configurable decoder includes a plurality of mode selection inputs, a plurality of address inputs, a plurality of logic level definition inputs, and a plurality of disable inputs. Various combinations of decoding functions are provided by the electrically configurable decoder in response to the mode selection inputs. A plurality of selection circuits selectively decodes various ones of the address inputs and mode selection inputs to produce signals which are applied to decode inputs and enable inputs of the basic decoder circuits. A logical "one" applied to a first one of the logic level definition inputs causes "high" and "low" voltage levels produced at the outputs of a first one of the basic decoder circuits to represent logical "ones" and "zeroes," respectively. A disable signal applied to one of the disable inputs of the electrically configurable decoder causes the outputs of the first basic decoder circuits to assume logical "zero" levels as determined by the first logic level definition input.
    • 一种电气可配置解码器,包括多个基本解码电路的可选配置的组合。 电可配置解码器包括多个模式选择输入,多个地址输入,多个逻辑电平定义输入和多个禁用输入。 响应于模式选择输入,电可配置解码器提供各种解码功能的组合。 多个选择电路选择性地解码地址输入和模式选择输入中的各种,以产生应用于解码输入和使能基本解码器电路的输入的信号。 应用于逻辑电平定义输入中的第一个逻辑电平定义输入的逻辑“1”导致在第一个基本解码器电路的输出处产生的“高”和“低”电压电平来表示逻辑“1”和“零” 分别。 施加到电可配置解码器的禁用输入之一的禁用信号使第一基本解码器电路的输出呈现由第一逻辑电平定义输入确定的逻辑“零”电平。