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    • 5. 发明授权
    • Circuit and method for processing an input signal
    • 用于处理输入信号的电路和方法
    • US08922719B2
    • 2014-12-30
    • US12039250
    • 2008-02-28
    • Gerd SpalinkBen Eitel
    • Gerd SpalinkBen Eitel
    • H04N5/00H04N5/455H03D3/00H03D3/02H03D3/24
    • H03D3/241
    • Circuit for processing an input signal based on at least one reference signal, comprising a phase locked loop demodulator configured to receive a speed control signal and said input signal and further configured to follow a frequency and/or a phase of said input signal at a speed, wherein said speed depends on said speed control signal; and a reference signal detector configured to determine said at least one reference signal and to set said speed by outputting said speed control signal to said phase locked loop demodulator, wherein, if said reference signal detector detects said at least one reference signal, said reference signal detector decreases said speed.
    • 一种用于基于至少一个参考信号处理输入信号的电路,包括:锁相环解调器,被配置为接收速度控制信号和所述输入信号,并进一步被配置为以一定的速度跟随所述输入信号的频率和/或相位 ,其中所述速度取决于所述速度控制信号; 以及参考信号检测器,被配置为通过将所述速度控制信号输出到所述锁相环解调器来确定所述至少一个参考信号并设置所述速度,其中如果所述参考信号检测器检测到所述至少一个参考信号,则所述参考信号 检测器降低所述速度。
    • 6. 发明授权
    • Cycle synchronization between interconnected sub-networks
    • 互连子网间的周期同步
    • US07184449B2
    • 2007-02-27
    • US09972208
    • 2001-10-05
    • Gerd Spalink
    • Gerd Spalink
    • H04J3/06
    • G06F1/14H04J3/0655H04L12/40078H04L12/4035
    • A method to perform a cycle synchronization between interconnected sub-networks, in which a reference node connected to one of the sub-networks transmits a respective cycle time information to cycle masters of all other sub-networks at recurring time instants, and the cycle masters of all other sub-networks adjust their cycle time accordingly. An adjustment of the cycle time within a cycle master is performed by determining a first time interval (Δt1, Δt1′) in-between two receptions of cycle time information from the reference node with an own clock, determining a second time interval (Δt2, Δt2′) in-between two corresponding transmissions of cycle time information from the reference node on basis of the received cycle time information, comparing the first time interval (Δt1, Δt1′) and the second time interval (Δt2, Δt2′), and adjusting the own cycle length according to the comparison result.
    • 一种在相互连接的子网之间执行周期同步的方法,其中连接到一个子网络的参考节点发送相应的周期时间信息,以循环时间周期的所有其他子网络的周期主站,以及循环主站 所有其他子网络相应地调整其周期时间。 通过确定在循环时间信息的两次接收之间的第一时间间隔(Deltat 1,Deltat 1&lt; 1&gt;)来执行循环主机内的循环时间的调整, 具有自己的时钟的参考节点,确定来自参考节点的循环时间信息的两个对应的传输之间的第二时间间隔(Deltat 2,Deltat 2&lt; 2&gt;) 基于接收到的周期时间信息,将第一时间间隔(Deltat1&lt; 1&gt;,Deltat1&lt; 1&gt;)与第二时间间隔(Deltat2&lt; ,Deltat <2> ),并根据比较结果调整自身的周期长度。
    • 7. 发明授权
    • Interface link layer device to build a distributed network
    • 接口链路层设备构建分布式网络
    • US07180904B2
    • 2007-02-20
    • US09751882
    • 2000-12-29
    • Gralf GaedekenPeter BuchnerGerd Spalink
    • Gralf GaedekenPeter BuchnerGerd Spalink
    • H04J3/00H04J3/16H04J3/22
    • H04L12/40058H04L12/2803H04L12/2832H04L12/2838H04L12/40071H04L12/40091H04L12/40097H04L12/40117H04L12/4625H04L12/6418H04L69/08
    • An interface link layer device of an interface which allows the interconnection of different networks to build a distributed network, The interface link layer routes complete data packets directly to another interface link layer device that serves the destination via uplink to accept a data packet from a first data bus that has a predetermined destination on a second data bus and to transmit the data packet via a transmission path to interface link layer device. The interface link layer also using downlink to output data packets received via the transmission path from another interface link layer device to a predetermined destination on the first data bus. Further, the interface link layer device is configured such that not all packets have to be transmitted via the interface on basis of an appropriate acknowledge code and response packet generation included in the interface link layer device.
    • 接口的接口链路层设备,允许不同网络互连建立分布式网络。接口链路层将完整的数据包直接传递到另一个通过上行链路服务目的地的接口链路层设备,以接收来自第一个 数据总线,其在第二数据总线上具有预定的目的地,并且经由传输路径将数据分组发送到接口链路层设备。 接口链路层还使用下行链路来输出经由从另一接口链路层设备到第一数据总线上的预定目的地的传输路径接收的数据分组。 此外,接口链路层设备被配置为使得不是所有分组都必须基于接口链路层设备中包括的适当的确认码和响应分组生成经由接口来发送。
    • 8. 发明申请
    • System for storing and rendering multimedia data
    • 用于存储和呈现多媒体数据的系统
    • US20050177626A1
    • 2005-08-11
    • US11051408
    • 2005-02-04
    • Volker FreiburgGerd SpalinkPeter Wagner
    • Volker FreiburgGerd SpalinkPeter Wagner
    • G06F12/00G11B20/10G11B27/10H04N5/93G06F15/16
    • G11B27/105G11B20/10
    • A system (1) for storing and rendering multimedia data comprises: a multimedia content archive (2) for storing multimedia data files (10, 13) to be rendered, a transforming algorithm archive (3) for storing transforming algorithm description files (12, 14, 15) comprising information for transforming multimedia data file (10, 13) of a first format into multimedia data files of a second format, respectively, wherein each stored multimedia data file (10, 13) is individually linked to at least one of said transforming algorithm description files (12, 14, 15), at least one rendering device (4a, 4b) being connected to said multimedia content archive (2) and said transforming algorithm archive (3), said at least one rendering device (4a, 4b) being capable of rendering a specific multimedia data file (10, 13) in dependence of transforming algorithm description files (12, 14, 15), to which said specific multimedia data file (10, 13) is linked to, respectively.
    • 一种用于存储和呈现多媒体数据的系统(1),包括:用于存储要呈现的多媒体数据文件(10,13)的多媒体内容存档(2),用于存储变换算法描述文件(12, 包括用于将第一格式的多媒体数据文件(10,13)分别转换为第二格式的多媒体数据文件的信息,其中每个存储的多媒体数据文件(10,13)被单独地链接到 所述变换算法描述文件(12,14,15),连接到所述多媒体内容存档(2)和所述变换算法存档(3)的至少一个渲染设备(4a,4b),所述至少一个渲染设备 (4a,4b)能够根据所述特定多媒体数据文件(10,13)链接到的变换算法描述文件(12,14,15)来呈现特定的多媒体数据文件(10,13) 分别。
    • 9. 发明授权
    • Packet synchronization detector
    • 分组同步检测器
    • US06816560B1
    • 2004-11-09
    • US09610460
    • 2000-07-05
    • Gerd Spalink
    • Gerd Spalink
    • H04L700
    • H04N21/4302H04L7/042H04L7/08H04N19/00H04N19/70H04N21/242
    • A packet synchronization detector for an incoming digital signal which includes a regularly repeated predetermined synchronization pattern which repetition rate defines the length of one transmission packet according to the present invention comprises a synchronization pattern detector (1) and several synchronization state machines (2, 31, . . . , 3n) which respectively determine whether or not one detected synchronization pattern with a respective position in regard to the length of one transmission frame has the correct repetition rate to determine whether or not lock has been achieved. Therefore, a very fast lock is achieved, since also in case of bit patterns that match to the synchronization byte, but that are not the synchronization byte no penalty time occurs to lock to the incoming digital signal.
    • 一种用于输入数字信号的分组同步检测器,其包括根据本发明的重复率定义一个传输分组的长度的规则重复的预定同步模式,包括同步模式检测器(1)和多个同步状态机(2,31, ...,3n),其分别确定一个检测到的与一个传输帧的长度相对应的位置的同步模式是否具有正确的重复率,以确定是否已经实现了锁定。 因此,实现非常快速的锁定,因为在与同步字节匹配的位模式的情况下,但是不是同步字节,因此锁定到输入数字信号不发生惩罚时间。