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1. 发明申请

US20070147387A1 INTERFACE LINK LAYER DEVICE FOR LONG DELAY CONNECTIONS 审中-公开
公开(公告)号：US20070147387A1
公开(公告)日：2007-06-28
申请号：US11683832
申请日：2007-03-08
申请人： Gerd Spalink , Gralf Gaedeken , Peter Buchner
发明人： Gerd Spalink , Gralf Gaedeken , Peter Buchner
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： G06F13/4072 , H04L12/462 , H04L12/64
摘要： An interface link layer device (1) to be connected in-between a first sub net-work (5) and a long delay link (3) to which at least one second sub network (4) is connected via another interface link layer device (2) is able to simulate or replace time critical messages of the at least one second sub network (4). To set-up a network with such interface link layer devices information about the configuration of the sub network (5; 4) connected to an interface link layer device (1; 2) is transmitted from said respective interface link layer device (1; 2 ) to all other interface link layer devices (2; 1) connected to said respective interface link layer device (1; 2) via the long delay link (3), whereafter a respective interface link layer device (2; 1) connected thereto which received information about the configuration of at least one other sub network (5; 4) is able to perform the necessary simulation.

2. 发明授权

US07180904B2 Interface link layer device to build a distributed network 失效
标题翻译：接口链路层设备构建分布式网络
公开(公告)号：US07180904B2
公开(公告)日：2007-02-20
申请号：US09751882
申请日：2000-12-29
申请人： Gralf Gaedeken , Peter Buchner , Gerd Spalink
发明人： Gralf Gaedeken , Peter Buchner , Gerd Spalink
IPC分类号： H04J3/00 , H04J3/16 , H04J3/22
CPC分类号： H04L12/40058 , H04L12/2803 , H04L12/2832 , H04L12/2838 , H04L12/40071 , H04L12/40091 , H04L12/40097 , H04L12/40117 , H04L12/4625 , H04L12/6418 , H04L69/08
摘要： An interface link layer device of an interface which allows the interconnection of different networks to build a distributed network, The interface link layer routes complete data packets directly to another interface link layer device that serves the destination via uplink to accept a data packet from a first data bus that has a predetermined destination on a second data bus and to transmit the data packet via a transmission path to interface link layer device. The interface link layer also using downlink to output data packets received via the transmission path from another interface link layer device to a predetermined destination on the first data bus. Further, the interface link layer device is configured such that not all packets have to be transmitted via the interface on basis of an appropriate acknowledge code and response packet generation included in the interface link layer device.
摘要翻译：接口的接口链路层设备，允许不同网络互连建立分布式网络。接口链路层将完整的数据包直接传递到另一个通过上行链路服务目的地的接口链路层设备，以接收来自第一个数据总线，其在第二数据总线上具有预定的目的地，并且经由传输路径将数据分组发送到接口链路层设备。接口链路层还使用下行链路来输出经由从另一接口链路层设备到第一数据总线上的预定目的地的传输路径接收的数据分组。此外，接口链路层设备被配置为使得不是所有分组都必须基于接口链路层设备中包括的适当的确认码和响应分组生成经由接口来发送。

3. 发明授权

US07454513B2 Interface link layer device for long delay connections 失效
标题翻译：用于长延迟连接的接口链路层设备
公开(公告)号：US07454513B2
公开(公告)日：2008-11-18
申请号：US09799748
申请日：2001-03-06
申请人： Gerd Spalink , Gralf Gaedeken , Peter Buchner
发明人： Gerd Spalink , Gralf Gaedeken , Peter Buchner
IPC分类号： G06F15/16 , G06F13/36 , H04L12/56
CPC分类号： G06F13/4072 , H04L12/462 , H04L12/64
摘要： An interface link layer device for use in a network having a first sub-network having one or more nodes, a second sub-network having one or more nodes and a long delay link via which the first and second sub-networks are connected. The interface link layer device configured to simulate time critical self-ID packets to be effected on the first sub-network based on received information about one or more nodes local to the second sub-network.
摘要翻译：一种用于具有具有一个或多个节点的第一子网络的网络中的接口链路层设备，具有一个或多个节点的第二子网络和连接所述第一和第二子网络的长延迟链路。接口链路层设备，被配置为基于接收到关于第二子网本地的一个或多个节点的信息来模拟在第一子网上实现的时间关键的自身ID分组。

4. 发明申请

US20070127470A1 INTERFACE LINK LAYER DEVICE TO BUILD A DISTRIBUTED NETWORK 审中-公开
标题翻译：接口连接层设备构建分布式网络
公开(公告)号：US20070127470A1
公开(公告)日：2007-06-07
申请号：US11674468
申请日：2007-02-13
申请人： Gralf Gaedeken , Peter Buchner , Gerd Spalink
发明人： Gralf Gaedeken , Peter Buchner , Gerd Spalink
IPC分类号： H04L12/56 , H04L12/54
CPC分类号： H04L12/40058 , H04L12/2803 , H04L12/2832 , H04L12/2838 , H04L12/40071 , H04L12/40091 , H04L12/40097 , H04L12/40117 , H04L12/4625 , H04L12/6418 , H04L69/08
摘要： An interface link layer device (1) of an interface which allows the interconnection of different networks to build a distributed network according to the present invention routes complete data packets directly to another interface link layer device (1) that serves the destination via uplink means (10, 11, 12, 13, 14, 17) to accept a data packet from a first data bus (2) that has a predetermined destination on a second data bus and to transmit it via said transmission path (3) to said other interface link layer device (1), and downlink means (20, 21) to output data packets received via said transmission path (3) from one other interface link layer device (1) to a predetermined destination on the first data bus (2). Furtheron, the interface link layer device according to the present invention introduces the concept that not all packets have to be transmitted via the interface on basis of an appropriate acknowledge code and response packet generation of an acknowledge/response means (18, 19) included in the interface link layer device. The present invention is in particular applicable to build up a disrtibuted network on basis of several IEEE 1394 networks that are interconnected via an interface consisting of a coaxial cable.
摘要翻译：根据本发明的允许不同网络互连构建分布式网络的接口的接口链路层设备（1）将完整数据分组直接路由到经由上行链路装置为目的地服务的另一接口链路层设备（1） 10,11,12,13,14,17）接收来自在第二数据总线上具有预定目的地的第一数据总线（2）的数据分组，并经由所述传输路径（3）将其发送到所述另一接口链路层设备（1）和下行链路装置（20,21），用于将经由所述传输路径（3）接收的数据分组从另一个接口链路层设备（1）输出到第一数据总线（2）上的预定目的地。此外，根据本发明的接口链路层设备引入了这样的概念：不是所有的分组必须经由接口发送，而是基于适当的确认码以及响应包生成包括在其中的确认/响应装置（18,19）接口链路层设备。本发明特别适用于在经由由同轴电缆组成的接口互连的多个IEEE 1394网络的基础上建立一个不协调的网络。

5. 发明授权

US5532753A Remote-controlled on-screen audio/video receiver control apparatus 失效
标题翻译：遥控屏幕音频/视频接收器控制装置
公开(公告)号：US5532753A
公开(公告)日：1996-07-02
申请号：US214569
申请日：1994-03-18
申请人： Peter Buchner , Gerd Spalink
发明人： Peter Buchner , Gerd Spalink
IPC分类号： G11B15/02 , G11B31/00 , H04N5/445 , H04Q9/00 , H04N5/50
CPC分类号： H04N21/485 , H04N5/44513 , H04N5/44543
摘要： An audio and/or video reproducing apparatus receives broadcast signals from broadcasting stations and a/v signals from an external device; processes the audio and/or video input signals in accordance with multiple processing functions; selects audio and/or video input signals for reproduction; reproduces sound and/or a video picture corresponding to the selected audio and/or video input signals; and includes a pointing device and a control device for generating a control picture signal and controlling the processing of signals and a display device for displaying a control picture corresponding to the control picture signal. The control picture includes a plurality of control areas and a pointer movable within the control picture in response to operation of the pointing device, with identifications of the broadcasting stations and the external device provided within certain control areas. The control device selectively modifies the control picture or one of the control areas or controls the processing of signals in accordance with one of the control areas pointed by the pointer. Audio and/or video input signals corresponding to one of the plurality of control areas displaying one of the identifications pointed by the pointer can be reproduced.
摘要翻译：音频和/或视频再现设备从广播站接收广播信号和从外部设备接收a / v信号; 根据多种处理功能处理音频和/或视频输入信号; 选择用于再现的音频和/或视频输入信号; 再现对应于所选音频和/或视频输入信号的声音和/或视频图像; 并且包括用于产生控制画面信号并控制信号处理的指示设备和控制设备以及用于显示与控制画面信号对应的控制画面的显示设备。响应于指示装置的操作，控制图像包括多个控制区域和可在控制图像内移动的指针，其中广播站和设置在特定控制区域内的外部设备的标识。控制装置根据指针指向的控制区域之一选择性地修改控制画面或控制区域中的一个或控制信号的处理。可以再现对应于显示由指针指示的标识之一的多个控制区域之一的音频和/或视频输入信号。

6. 发明授权

US08922719B2 Circuit and method for processing an input signal 有权
标题翻译：用于处理输入信号的电路和方法
公开(公告)号：US08922719B2
公开(公告)日：2014-12-30
申请号：US12039250
申请日：2008-02-28
申请人： Gerd Spalink , Ben Eitel
发明人： Gerd Spalink , Ben Eitel
IPC分类号： H04N5/00 , H04N5/455 , H03D3/00 , H03D3/02 , H03D3/24
CPC分类号： H03D3/241
摘要： Circuit for processing an input signal based on at least one reference signal, comprising a phase locked loop demodulator configured to receive a speed control signal and said input signal and further configured to follow a frequency and/or a phase of said input signal at a speed, wherein said speed depends on said speed control signal; and a reference signal detector configured to determine said at least one reference signal and to set said speed by outputting said speed control signal to said phase locked loop demodulator, wherein, if said reference signal detector detects said at least one reference signal, said reference signal detector decreases said speed.
摘要翻译：一种用于基于至少一个参考信号处理输入信号的电路，包括：锁相环解调器，被配置为接收速度控制信号和所述输入信号，并进一步被配置为以一定的速度跟随所述输入信号的频率和/或相位，其中所述速度取决于所述速度控制信号; 以及参考信号检测器，被配置为通过将所述速度控制信号输出到所述锁相环解调器来确定所述至少一个参考信号并设置所述速度，其中如果所述参考信号检测器检测到所述至少一个参考信号，则所述参考信号检测器降低所述速度。

7. 发明申请

US20110242429A1 METHOD AND RECEIVER FOR DEMODULATION 失效
标题翻译：用于解调的方法和接收器
公开(公告)号：US20110242429A1
公开(公告)日：2011-10-06
申请号：US12864573
申请日：2008-12-23
申请人： Rolf Noethlings , Gerd Spalink
发明人： Rolf Noethlings , Gerd Spalink
IPC分类号： H04N5/455
CPC分类号： H04L27/00 , G10L19/005 , H04L27/22 , H04L27/38
摘要： A method of demodulation includes determining samples of a modulated analogue audio signal; determining at least one distorted sample of the samples depending on the signal quality of the modulated analogue audio signal; and replacing the distorted sample.
摘要翻译：一种解调方法包括：确定调制模拟音频信号的样本; 根据所调制的模拟音频信号的信号质量来确定样本的至少一个失真采样; 并替换失真的样品。

8. 发明授权

US07184449B2 Cycle synchronization between interconnected sub-networks 有权
标题翻译：互连子网间的周期同步
公开(公告)号：US07184449B2
公开(公告)日：2007-02-27
申请号：US09972208
申请日：2001-10-05
申请人： Gerd Spalink
发明人： Gerd Spalink
IPC分类号： H04J3/06
CPC分类号： G06F1/14 , H04J3/0655 , H04L12/40078 , H04L12/4035
摘要： A method to perform a cycle synchronization between interconnected sub-networks, in which a reference node connected to one of the sub-networks transmits a respective cycle time information to cycle masters of all other sub-networks at recurring time instants, and the cycle masters of all other sub-networks adjust their cycle time accordingly. An adjustment of the cycle time within a cycle master is performed by determining a first time interval (Δt1, Δt1′) in-between two receptions of cycle time information from the reference node with an own clock, determining a second time interval (Δt2, Δt2′) in-between two corresponding transmissions of cycle time information from the reference node on basis of the received cycle time information, comparing the first time interval (Δt1, Δt1′) and the second time interval (Δt2, Δt2′), and adjusting the own cycle length according to the comparison result.
摘要翻译：一种在相互连接的子网之间执行周期同步的方法，其中连接到一个子网络的参考节点发送相应的周期时间信息，以循环时间周期的所有其他子网络的周期主站，以及循环主站所有其他子网络相应地调整其周期时间。通过确定在循环时间信息的两次接收之间的第一时间间隔（Deltat 1，Deltat 1＆lt; 1＆gt;）来执行循环主机内的循环时间的调整，具有自己的时钟的参考节点，确定来自参考节点的循环时间信息的两个对应的传输之间的第二时间间隔（Deltat 2，Deltat 2＆lt; 2＆gt;）基于接收到的周期时间信息，将第一时间间隔（Deltat1＆lt; 1＆gt;，Deltat1＆lt; 1＆gt;）与第二时间间隔（Deltat2＆lt; ，Deltat <2> ），并根据比较结果调整自身的周期长度。

9. 发明申请

US20050177626A1 System for storing and rendering multimedia data 失效
标题翻译：用于存储和呈现多媒体数据的系统
公开(公告)号：US20050177626A1
公开(公告)日：2005-08-11
申请号：US11051408
申请日：2005-02-04
申请人： Volker Freiburg , Gerd Spalink , Peter Wagner
发明人： Volker Freiburg , Gerd Spalink , Peter Wagner
IPC分类号： G06F12/00 , G11B20/10 , G11B27/10 , H04N5/93 , G06F15/16
CPC分类号： G11B27/105 , G11B20/10
摘要： A system (1) for storing and rendering multimedia data comprises: a multimedia content archive (2) for storing multimedia data files (10, 13) to be rendered, a transforming algorithm archive (3) for storing transforming algorithm description files (12, 14, 15) comprising information for transforming multimedia data file (10, 13) of a first format into multimedia data files of a second format, respectively, wherein each stored multimedia data file (10, 13) is individually linked to at least one of said transforming algorithm description files (12, 14, 15), at least one rendering device (4a, 4b) being connected to said multimedia content archive (2) and said transforming algorithm archive (3), said at least one rendering device (4a, 4b) being capable of rendering a specific multimedia data file (10, 13) in dependence of transforming algorithm description files (12, 14, 15), to which said specific multimedia data file (10, 13) is linked to, respectively.
摘要翻译：一种用于存储和呈现多媒体数据的系统（1），包括：用于存储要呈现的多媒体数据文件（10,13）的多媒体内容存档（2），用于存储变换算法描述文件（12，包括用于将第一格式的多媒体数据文件（10,13）分别转换为第二格式的多媒体数据文件的信息，其中每个存储的多媒体数据文件（10,13）被单独地链接到所述变换算法描述文件（12,14,15），连接到所述多媒体内容存档（2）和所述变换算法存档（3）的至少一个渲染设备（4a，4b），所述至少一个渲染设备（4a，4b）能够根据所述特定多媒体数据文件（10,13）链接到的变换算法描述文件（12,14,15）来呈现特定的多媒体数据文件（10,13）分别。

10. 发明授权

US06816560B1 Packet synchronization detector 失效
标题翻译：分组同步检测器
公开(公告)号：US06816560B1
公开(公告)日：2004-11-09
申请号：US09610460
申请日：2000-07-05
申请人： Gerd Spalink
发明人： Gerd Spalink
IPC分类号： H04L700
CPC分类号： H04N21/4302 , H04L7/042 , H04L7/08 , H04N19/00 , H04N19/70 , H04N21/242
摘要： A packet synchronization detector for an incoming digital signal which includes a regularly repeated predetermined synchronization pattern which repetition rate defines the length of one transmission packet according to the present invention comprises a synchronization pattern detector (1) and several synchronization state machines (2, 31, . . . , 3n) which respectively determine whether or not one detected synchronization pattern with a respective position in regard to the length of one transmission frame has the correct repetition rate to determine whether or not lock has been achieved. Therefore, a very fast lock is achieved, since also in case of bit patterns that match to the synchronization byte, but that are not the synchronization byte no penalty time occurs to lock to the incoming digital signal.
摘要翻译：一种用于输入数字信号的分组同步检测器，其包括根据本发明的重复率定义一个传输分组的长度的规则重复的预定同步模式，包括同步模式检测器（1）和多个同步状态机（2,31， ...，3n），其分别确定一个检测到的与一个传输帧的长度相对应的位置的同步模式是否具有正确的重复率，以确定是否已经实现了锁定。因此，实现非常快速的锁定，因为在与同步字节匹配的位模式的情况下，但是不是同步字节，因此锁定到输入数字信号不发生惩罚时间。

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