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1. 发明授权

US08392636B2 Virtual multiple instance extended finite state machines with wait rooms and/or wait queues 失效
标题翻译：具有等待室和/或等待队列的虚拟多实例扩展有限状态机
公开(公告)号：US08392636B2
公开(公告)日：2013-03-05
申请号：US12546852
申请日：2009-08-25
申请人： Rolf K. Fritz , Ulrich Mayer , Thomas Schlipf , Stephan Christopher Smith
发明人： Rolf K. Fritz , Ulrich Mayer , Thomas Schlipf , Stephan Christopher Smith
IPC分类号： G06F3/00 , G06F5/00 , G06F7/38 , H03K19/173
CPC分类号： H04L49/90
摘要： A method and apparatus for processing data by a pipeline of a virtual multiple instance extended finite state machine (VMI EFSM). An input token is selected to enter the pipeline. The input token includes a reference to an EFSM instance, an extended command, and an operation code. The EFSM instance requires the resource to be available to generate an output token from the input token. In response to receiving an indication that the resource is unavailable, the input token is sent to a wait room or an initiative token containing the reference and the operation code is sent to a wait queue, and the output token is not generated. Without stalling and restarting the pipeline, another input token is processed in the pipeline while the resource is unavailable and while the input token is in the wait room or the initiative token is in the wait queue.
摘要翻译：一种用于通过虚拟多实例扩展有限状态机（VMI EFSM）的流水线处理数据的方法和装置。选择输入令牌进入管道。输入令牌包括对EFSM实例的引用，扩展命令和操作代码。 EFSM实例需要资源可用于从输入令牌生成输出令牌。响应于接收到资源不可用的指示，将输入令牌发送到等待室或包含引用的主动令牌，并且将操作代码发送到等待队列，并且不生成输出令牌。在不停止并重新启动流水线的情况下，另一个输入令牌在流水线中处理，而资源不可用，而输入令牌位于等待室或主动令牌处于等待队列中。

2. 发明申请

US20110055842A1 VIRTUAL MULTIPLE INSTANCE EXTENDED FINITE STATE MACHINES WITH WAIT ROOMS AND/OR WAIT QUEUES 失效
标题翻译：虚拟多个实例扩展有限状态机与等待室和/或等待队列
公开(公告)号：US20110055842A1
公开(公告)日：2011-03-03
申请号：US12546852
申请日：2009-08-25
申请人： Rolf K. Fritz , Ulrich Mayer , Thomas Schlipf , Stephan Christopher Smith
发明人： Rolf K. Fritz , Ulrich Mayer , Thomas Schlipf , Stephan Christopher Smith
IPC分类号： G06F9/46
CPC分类号： H04L49/90
摘要： A method and apparatus for processing data by a pipeline of a virtual multiple instance extended finite state machine (VMI EFSM). An input token is selected to enter the pipeline. The input token includes a reference to an EFSM instance, an extended command, and an operation code. The EFSM instance requires the resource to be available to generate an output token from the input token. In response to receiving an indication that the resource is unavailable, the input token is sent to a wait room or an initiative token containing the reference and the operation code is sent to a wait queue, and the output token is not generated. Without stalling and restarting the pipeline, another input token is processed in the pipeline while the resource is unavailable and while the input token is in the wait room or the initiative token is in the wait queue.
摘要翻译：一种用于通过虚拟多实例扩展有限状态机（VMI EFSM）的流水线处理数据的方法和装置。选择输入令牌进入管道。输入令牌包括对EFSM实例的引用，扩展命令和操作代码。 EFSM实例需要资源可用于从输入令牌生成输出令牌。响应于接收到资源不可用的指示，将输入令牌发送到等待室或包含引用的主动令牌，并且将操作代码发送到等待队列，并且不生成输出令牌。在不停止并重新启动流水线的情况下，另一个输入令牌在流水线中处理，而资源不可用，而输入令牌位于等待室或主动令牌处于等待队列中。

3. 发明授权

US07683665B1 Multiple parallel programmable finite state machines using a shared transition table 失效
标题翻译：使用共享转换表的多个并行可编程有限状态机
公开(公告)号：US07683665B1
公开(公告)日：2010-03-23
申请号：US12427559
申请日：2009-04-21
申请人： Rolf Fritz , Ulrich Mayer , Thomas Schlipf , Christopher S Smith
发明人： Rolf Fritz , Ulrich Mayer , Thomas Schlipf , Christopher S Smith
IPC分类号： H03K19/173
CPC分类号： G05B19/042 , G05B2219/23289
摘要： A system and method of implementing multiple programmable finite state machines using a shared transition table is disclosed, the method including forming a plurality of finite state machine cores such that an amount of the plurality of finite state machine cores is unchangeable, forming a state transition array, and forming a routing network such that the forming the plurality of associated state transition elements is realized.
摘要翻译：公开了一种使用共享转换表实现多个可编程有限状态机的系统和方法，该方法包括形成多个有限状态机核，使得多个有限状态机核的数量不可改变，形成状态转移阵列并且形成路由网络，从而实现形成多个相关联的状态转换元件。

4. 发明申请

US20100332798A1 Digital Processor and Method 审中-公开
标题翻译：数字处理器和方法
公开(公告)号：US20100332798A1
公开(公告)日：2010-12-30
申请号：US12825402
申请日：2010-06-29
申请人： Martin Doerr , Hubert Eichner , Markus Kaltenbach , Volker Koch , Ulrich Mayer , Thomas Pflueger , Thomas Schlipf , Cordt Starke , Jan Van Lunteren
发明人： Martin Doerr , Hubert Eichner , Markus Kaltenbach , Volker Koch , Ulrich Mayer , Thomas Pflueger , Thomas Schlipf , Cordt Starke , Jan Van Lunteren
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： G06F9/3012 , G06F9/3828 , G06F9/3891
摘要： A processor subunit for a processor for processing data. The processor subunit includes registers, and at least one functional unit for executing instructions on data. One or more registers of the registers are connected to an input of the at least one functional unit, where each register connected to the input of the at least one functional unit which has an input multiplexer. One or more registers of the registers are connected to an output of the at least one functional unit, where each register connected to the output of the at least one functional unit which has an input multiplexer. At least one output bus is connected to at least one register. At least one input bus is connected to at least one register. The processor subunit may be used in a processor, which may be used in a data streaming accelerator.
摘要翻译：用于处理数据的处理器的处理器子单元。处理器子单元包括寄存器和用于执行数据指令的至少一个功能单元。寄存器的一个或多个寄存器被连接到至少一个功能单元的输入，其中每个寄存器连接到具有输入多路复用器的至少一个功能单元的输入。寄存器的一个或多个寄存器被连接到至少一个功能单元的输出，其中每个寄存器连接到具有输入多路复用器的至少一个功能单元的输出端。至少一个输出总线连接到至少一个寄存器。至少一个输入总线连接到至少一个寄存器。处理器子单元可以用在可以在数据流加速器中使用的处理器中。

5. 发明授权

US09891922B2 Selectively blocking branch prediction for a predetermined number of instructions 有权
公开(公告)号：US09891922B2
公开(公告)日：2018-02-13
申请号：US13524402
申请日：2012-06-15
申请人： James J. Bonanno , Ulrich Mayer , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
发明人： James J. Bonanno , Ulrich Mayer , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/38 , G06F9/30076 , G06F9/3844 , G06F9/3848
摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.

6. 发明授权

US09235419B2 Branch target buffer preload table 有权
公开(公告)号：US09235419B2
公开(公告)日：2016-01-12
申请号：US13492997
申请日：2012-06-11
申请人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
发明人： James J. Bonanno , Ulrich Mayer , Brian R. Prasky
IPC分类号： G06F9/32 , G06F9/38
CPC分类号： G06F9/3806
摘要： Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry.

7. 发明申请

US20130339683A1 INSTRUCTION FILTERING 有权
标题翻译：指令过滤
公开(公告)号：US20130339683A1
公开(公告)日：2013-12-19
申请号：US13523170
申请日：2012-06-14
申请人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
发明人： James J. Bonanno , Adam B. Collura , Ulrich Mayer , Brian R. Prasky , Anthony Saporito , Chung-Lung K. Shum
IPC分类号： G06F9/30
CPC分类号： G06F9/3844 , G06F9/30 , G06F9/30047 , G06F9/3005 , G06F9/3806 , G06F9/3836
摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.
摘要翻译：实施例涉及指令过滤。一个方面包括用于指令过滤的系统。该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。基于标记的指令文本来防止跟踪指令逻辑块的动作。

8. 发明授权

US08518720B2 UV irradiance monitoring in semiconductor processing using a temperature dependent signal 有权
标题翻译：使用温度依赖信号的半导体处理中的紫外线辐照度监测
公开(公告)号：US08518720B2
公开(公告)日：2013-08-27
申请号：US12854995
申请日：2010-08-12
申请人： Ulrich Mayer , Thorsten Schepers
发明人： Ulrich Mayer , Thorsten Schepers
IPC分类号： H01L21/66
CPC分类号： H01L21/3105 , H01L21/67115 , H01L21/67248
摘要： In a UV process tool for semiconductor processing, a temperature-dependent signal may be used as a monitor signal for determining the momentary irradiance of the UV radiation source. Consequently, a fast and reliable monitoring and/or controlling of the irradiance of UV process tools may be accomplished.
摘要翻译：在用于半导体处理的UV处理工具中，可以使用温度依赖信号作为用于确定UV辐射源的瞬时辐照度的监视信号。因此，可以实现对UV处理工具的辐照度的快速和可靠的监测和/或控制。

9. 发明授权

US08135960B2 Multiprocessor electronic circuit including a plurality of processors and electronic data processing system 有权
标题翻译：多处理器电子电路包括多个处理器和电子数据处理系统
公开(公告)号：US08135960B2
公开(公告)日：2012-03-13
申请号：US12248549
申请日：2008-10-09
申请人： Thomas Koehler , Thomas Fuchs , Ulrich Mayer , Chung-Lung Kevin Shum , Scott Barnett Swaney
发明人： Thomas Koehler , Thomas Fuchs , Ulrich Mayer , Chung-Lung Kevin Shum , Scott Barnett Swaney
IPC分类号： G06F12/14
CPC分类号： G06F21/72
摘要： A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.
摘要翻译：公开了一种包括这种电路的多处理器电子电路和电子数据处理系统，用于降低具有加密功能的多处理器系统的功耗和芯片面积消耗。在一个实施例中，多处理器电子电路包括多个处理器，包括多个输入/输出缓冲器对和两个加密引擎，密码引擎和哈希引擎以及相关控制逻辑的单个密码处理单元。

10. 发明申请

US20110320743A1 MEMORY ORDERED STORE SYSTEM IN A MULTIPROCESSOR COMPUTER SYSTEM 有权
标题翻译：多处理器计算机系统中的存储订单存储系统
公开(公告)号：US20110320743A1
公开(公告)日：2011-12-29
申请号：US12822331
申请日：2010-06-24
申请人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
发明人： Norbert Hagspiel , Matthias Klein , Ulrich Mayer , Robert J. Sonnelitter, III , Gary E. Strait , Hanno Ulrich
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F9/3842 , G06F9/528 , G06F12/0828 , G06F12/0831 , G06F12/0862 , G06F12/1054 , G06F2212/1016 , G06F2212/507 , G06F2212/621
摘要： A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory.
摘要翻译：提供了一种用于以快速的顺序将数据存储在计算机系统的存储器中的系统和计算机实现的方法。该方法包括向存储器启动第一个存储。启动等待计数器。当等待计数器到期时，第二家存储器被推测启动。当第二个存储在第一个存储到存储器之前实现相关性时，第二个存储器的存储被取消。

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