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1. 发明授权

US06993694B1 Deterministic bist architecture including MISR filter 有权
标题翻译：确定性bist架构，包括MISR过滤器
公开(公告)号：US06993694B1
公开(公告)日：2006-01-31
申请号：US10117747
申请日：2002-04-05
申请人： Rohit Kapur , Thomas W. Williams , Tony Taylor , Peter Wohl , John A. Waicukauski
发明人： Rohit Kapur , Thomas W. Williams , Tony Taylor , Peter Wohl , John A. Waicukauski
IPC分类号： G01R31/28 , G01R31/08
CPC分类号： G01R31/318547 , G01R31/318558
摘要： A filter for preventing uncertain bits output by test scan chains from being provided to a MISR is provided. The filter can include a gating structure for receiving a bit from a scan chain and control circuitry for providing a predetermined signal to the gating structure if the bit is an uncertain bit. In one embodiment, the gating structure can include a logic gate, such as an AND or an OR gate. The control circuitry can include components substantially similar to the pattern generator providing signals to the scan chain. For example, the control circuitry can include an LFSR and a PRPG shadow for loading the LFSR. In one embodiment, the control circuitry can further include a phase-shifter for receiving inputs from the LFSR and providing outputs to the gating structure.
摘要翻译：提供了一种用于防止测试扫描链输出的不确定位提供给MISR的滤波器。滤波器可以包括用于从扫描链接收比特的选通结构和用于如果该比特是不确定比特，则向选通结构提供预定信号的控制电路。在一个实施例中，门控结构可以包括逻辑门，诸如AND或OR门。控制电路可以包括与向扫描链提供信号的图案发生器基本相似的组件。例如，控制电路可以包括用于加载LFSR的LFSR和PRPG阴影。在一个实施例中，控制电路还可以包括用于接收来自LFSR的输入并向门控结构提供输出的移相器。

2. 发明申请

US20080256497A1 Scan compression circuit and method of design therefor 有权
标题翻译：扫描压缩电路及其设计方法
公开(公告)号：US20080256497A1
公开(公告)日：2008-10-16
申请号：US11807119
申请日：2007-05-25
申请人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
发明人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
IPC分类号： H03K19/173 , G06F17/50
CPC分类号： H03M7/30 , G06F17/505 , G06F2217/14
摘要： A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.
摘要翻译：基于扫描的电路包括通过多个观察逻辑实现的选择器。每个观察逻辑耦合到扫描链以接收要提供给组合式压缩机的数据。每个观察逻辑还耦合到组合压缩机的相应组输入线中的单个输入线，以选择性地从耦合的扫描链提供数据。每个观察逻辑可以耦合到相应组中的附加输入线（如果存在）。在（a）透明模式中，选择器可以在每个移位的基础上操作，其中数据被提供给所有输入线，并且（b）几个直接模式，其中来自仅一个扫描链的数据仅在每个压缩器输出处被提供而不重叠。

3. 发明授权

US07814444B2 Scan compression circuit and method of design therefor 有权
标题翻译：扫描压缩电路及其设计方法
公开(公告)号：US07814444B2
公开(公告)日：2010-10-12
申请号：US11807119
申请日：2007-05-25
申请人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
发明人： Peter Wohl , John A. Waicukauski , Sanjay Ramnath , Rohit Kapur , Thomas W. Williams
IPC分类号： G06F17/50
CPC分类号： H03M7/30 , G06F17/505 , G06F2217/14
摘要： A scan-based circuit includes a selector that is implemented by multiple observation logics. Each observation logic is coupled to a scan chain to receive data to be supplied to a combinational compressor. Each observation logic is also coupled to a single input line in a corresponding group of input lines of the combinational compressor, to selectively supply data from the coupled scan chain. Each observation logic may be coupled to additional input lines (if present) in the corresponding group. The selector is operable on a per-shift basis in (a) transparent mode wherein data is supplied to all input lines and (b) several direct modes wherein data from only one scan chain is supplied at each compressor output without overlap.
摘要翻译：基于扫描的电路包括通过多个观察逻辑实现的选择器。每个观察逻辑耦合到扫描链以接收要提供给组合式压缩机的数据。每个观察逻辑还耦合到组合压缩机的相应组输入线中的单个输入线，以选择性地从耦合的扫描链提供数据。每个观察逻辑可以耦合到相应组中的附加输入线（如果存在）。在（a）透明模式中，选择器可以在每个移位的基础上操作，其中数据被提供给所有输入线，并且（b）几个直接模式，其中来自仅一个扫描链的数据仅在每个压缩器输出处被提供而不重叠。

4. 发明授权

US06807646B1 System and method for time slicing deterministic patterns for reseeding in logic built-in self-test 有权
标题翻译：用于时间分片的系统和方法用于逻辑内置自检中的重新采样的确定性模式
公开(公告)号：US06807646B1
公开(公告)日：2004-10-19
申请号：US10091614
申请日：2002-03-04
申请人： Thomas W. Williams , Peter Wohl , John A. Waicukauski , Rohit Kapur
发明人： Thomas W. Williams , Peter Wohl , John A. Waicukauski , Rohit Kapur
IPC分类号： G06F1100
CPC分类号： G01R31/318307 , G01R31/318328
摘要： A system and method for time slicing deterministic patterns for reseeding in logic built-in self-test (BIST). The known properties of a linear feedback shift register (LFSR) and an associated set of channels are used in conjunction with a desired deterministic test pattern to create one or more seeds which can be used by the LFSR to generate the test pattern. The test pattern is divided into a number of segments, with each segment having a specific number of “care” bits. The number of shifts required to fill a segment using a particular seed is stored along with the seed as a seed lifetime. During testing, each deterministic test pattern is generated by loading a seed into the LFSR and cycling the LFSR in accordance with the lifetime of the seed. The seed lifetimes may have different values, and multiple seeds may be used in the generation of a single test pattern, or a single seed may be used to generate care bits of multiple test patterns.
摘要翻译：用于在逻辑内置自检（BIST）中时间切片确定性模式以重新进给的系统和方法。线性反馈移位寄存器（LFSR）和关联的一组通道的已知属性与期望的确定性测试模式结合使用以创建一个或多个可由LFSR用于生成测试模式的种子。测试图案被分成多个段，每个段具有特定数量的“关心”位。使用特定种子填充段所需的班次数与种子一起作为种子生存期一起存储。在测试期间，通过将种子加载到LFSR中并根据种子的寿命循环LFSR来产生每个确定性测试模式。种子寿命可以具有不同的值，并且可以在生成单个测试图案时使用多个种子，或者可以使用单个种子来生成多个测试图案的护理位。

5. 发明授权

US06950974B1 Efficient compression and application of deterministic patterns in a logic BIST architecture 有权
标题翻译：逻辑BIST架构中的确定性模式的有效压缩和应用
公开(公告)号：US06950974B1
公开(公告)日：2005-09-27
申请号：US09950292
申请日：2001-09-07
申请人： Peter Wohl , John A. Waicukauski , Thomas W. Williams
发明人： Peter Wohl , John A. Waicukauski , Thomas W. Williams
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318547 , G01R31/318558
摘要： Deterministic ATPG test coverage is provided in a logic BIST architecture while reducing test application time and test data volume, as compared to deterministic ATPG patterns. The logic BIST architecture can include a PRPG shadow operatively coupled to a PRPG circuit. The PRPG shadow allows re-seeding of the PRPG circuit with zero cycle overhead. Two compressions can be provided. In a first compression, multiple tests for faults are compressed into one pattern. In a second compression, multiple deterministic ATPG patterns can be compressed into one seed. All patterns provided from the PRPG can be controlled by these seeds so that all care bits are properly set, while all other scan cells are set to pseudo-random values from the PRPG. In this manner, the PRPG can rapidly deliver highly pertinent data to the scan chains of the device under test.
摘要翻译：与确定性ATPG模式相比，确定性ATPG测试覆盖在逻辑BIST架构中提供，同时减少测试应用时间和测试数据量。逻辑BIST架构可以包括可操作地耦合到PRPG电路的PRPG阴影。 PRPG阴影允许以零周期开销重新种植PRPG电路。可以提供两个按压。在第一次压缩中，将多个故障测试压缩成一个模式。在第二次压缩中，可以将多个确定性ATPG模式压缩成一个种子。从PRPG提供的所有图案都可以由这些种子进行控制，以便所有护理位都被正确设置，而所有其他扫描单元都被设置为来自PRPG的伪随机值。以这种方式，PRPG可以快速向被测设备的扫描链提供高度相关的数据。

6. 发明授权

US06385750B1 Method and system for controlling test data volume in deterministic test pattern generation 有权
标题翻译：用于在确定性测试模式生成中控制测试数据量的方法和系统
公开(公告)号：US06385750B1
公开(公告)日：2002-05-07
申请号：US09387865
申请日：1999-09-01
申请人： Rohit Kapur , Thomas W. Williams , John Waicukauski , Peter Wohl
发明人： Rohit Kapur , Thomas W. Williams , John Waicukauski , Peter Wohl
IPC分类号： G06F1100
CPC分类号： G01R31/31813
摘要： A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T. Based on the fault propagation information, test points are selectively inserted to maximize the fault coverage of the set of test patterns, T. In one embodiment, the nets to which most untested faults propagate are selected for test point insertion. The number of test points selected may be determined by user-defined parameters. These steps are then repeated for another set of set patterns until the desired fault coverage is achieved. By adding test points, the fault coverage of the test patterns is significantly improved, thus reducing the test data volume.
摘要翻译：一种改进测试矢量故障覆盖的方法和系统，用于测试集成电路。本发明还提供了一种通过以成本有效的方式插入测试点来减少测试集成电路所需的确定性测试向量的数量的方法和系统。根据本发明的实施例，初始化具有集成电路设计的所有潜在故障的故障列表，并将所有潜在故障标记为不可测。产生一组用于测试几个潜在故障的测试模式T。然后利用测试图案T对集成电路设计进行故障模拟处理，以标记未测试的故障。在故障模拟期间，监控故障传播，以确定传播故障的设计网络。还监测故障传播中断的网络（例如，去敏化）。该信息是通过一组测试模式T收集的。根据故障传播信息，选择性地插入测试点，以最大化测试模式集合T的故障覆盖。在一个实施例中，最未经测试的故障的网络选择传播以进行测试点插入。所选择的测试点的数量可以由用户定义的参数确定。然后对另一组设置模式重复这些步骤，直到实现所需的故障覆盖。通过添加测试点，测试模式的故障覆盖率显着提高，从而降低测试数据量。

7. 发明授权

US06453437B1 Method and system for performing transition fault simulation along long circuit paths for high-quality automatic test pattern generation 有权
标题翻译：用于高质量自动测试图形生成的长电路路径进行转换故障模拟的方法和系统
公开(公告)号：US06453437B1
公开(公告)日：2002-09-17
申请号：US09348712
申请日：1999-07-01
申请人： Rohit Kapur , Thomas W. Williams , John Waicukauski , Peter Wohl
发明人： Rohit Kapur , Thomas W. Williams , John Waicukauski , Peter Wohl
IPC分类号： G01R3128
CPC分类号： G06F11/263 , G01R31/318342
摘要： A method for generating a test pattern for use in testing an integrated circuit device. The computer implemented steps of receiving and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the netlist simulation, a set of circuit paths for each fault of the plurality of faults within the netlist specification is determined. From this set of paths, respective longest paths for each fault is determined. Using an ATPG (automatic test pattern generation) process, a test vector is determined for the first fault. Transition fault simulation is then performed on the first fault by applying the test vector to a first path through the first fault, wherein the first path is the longest path traversing through the first fault as determined by the ATPG process. Responsive to the transition fault simulation, a second fault that is fortuitously detected by the test vector as applied to a second path traversing through the second fault is identified. The test vector is credited with detecting the first fault, and, provided the second path is the longest path that traverses through the second fault, the test vector is credited with detecting the second fault. If the second path is not the longest path, a test vector is generated in a subsequent iteration of the method. In so doing, the method ensures transition faults are detected along long paths as opposed to short paths, thereby improving test quality.
摘要翻译：一种用于产生用于测试集成电路器件的测试图案的方法。计算机实现在计算机存储器单元中接收和存储网表规范的步骤，以及使用计算机实现的合成系统来模拟网表。使用网表模拟，确定网表规范内的多个故障的每个故障的一组电路路径。从这组路径中，确定每个故障的相应最长路径。使用ATPG（自动测试模式生成）过程，确定第一个故障的测试向量。然后通过将测试向量应用于通过第一故障的第一路径，对第一故障进行过渡故障模拟，其中第一路径是通过ATPG过程确定的穿过第一故障的最长路径。响应于过渡故障模拟，识别出应用于穿过第二故障的第二路径的由测试矢量偶然检测到的第二故障。测试矢量被检测到第一个故障，并且如果第二个路径是穿过第二个故障的最长路径，则测试向量被检测到第二个故障。如果第二条路径不是最长路径，则在该方法的后续迭代中生成测试向量。在这样做的过程中，该方法可以确保沿短路径沿长路径检测到过渡故障，从而提高测试质量。

8. 发明申请

US20080141188A1 Method and apparatus for limiting power dissipation in test 有权
标题翻译：测试中限制功耗的方法和装置
公开(公告)号：US20080141188A1
公开(公告)日：2008-06-12
申请号：US11635155
申请日：2006-12-07
申请人： Rohit Kapur , Thomas W. Williams
发明人： Rohit Kapur , Thomas W. Williams
IPC分类号： G06F19/00 , G06F17/50
CPC分类号： G01R31/318572
摘要： An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.
摘要翻译：实施例提供了一种用于测试电路的系统。在操作期间，系统将输入值扫描到第一组触发器中。第一组触发器的输出与待测电路的输入耦合，电路的输出与一组多路复用器的输入耦合，并且多路复用器组的输出与输入端耦合的第二组触发器。接下来，系统使用段选择电路配置多路复用器组，其使得电路的输出与第二组触发器的输入耦合。系统然后使用第二组触发器捕获电路的输出值。接下来，系统使用第二组触发器扫描电路的输出值。最后，系统使用输出值确定芯片是否有故障。

9. 发明申请

US20100223516A1 Dynamically Reconfigurable Shared Scan-In Test Architecture 有权
公开(公告)号：US20100223516A1
公开(公告)日：2010-09-02
申请号：US12779018
申请日：2010-05-12
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

10. 发明授权

US07774663B2 Dynamically reconfigurable shared scan-in test architecture 有权
公开(公告)号：US07774663B2
公开(公告)日：2010-08-10
申请号：US12500296
申请日：2009-07-09
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

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