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1. 发明授权

US08464115B2 Fully X-tolerant, very high scan compression scan test systems and techniques 有权
标题翻译：全X容忍，非常高的扫描压缩扫描测试系统和技术
公开(公告)号：US08464115B2
公开(公告)日：2013-06-11
申请号：US13172752
申请日：2011-06-29
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/318547
摘要： Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
摘要翻译：扫描测试和扫描压缩是实现成本降低和出货质量的关键。更复杂设计中的新缺陷类型需要增加压缩。然而，未知（X）值的增加的密度降低了有效压缩。扫描压缩方法可以为未知值的任何密度实现非常高的压缩和全覆盖。所描述的技术可以完全集成在测试设计（DFT）和自动测试模式生成（ATPG）流程中。在工业设计中使用这些技术的结果表明与其他方法相比是一致和可预测的优势。

2. 发明申请

US20110258503A1 Fully X-tolerant, Very High Scan Compression Scan Test Systems And Techniques 有权
标题翻译：全X容忍，非常高的扫描压缩扫描测试系统和技术
公开(公告)号：US20110258503A1
公开(公告)日：2011-10-20
申请号：US13172752
申请日：2011-06-29
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177 , G01R31/318547
摘要： Scan testing and scan compression are key to realizing cost reduction and shipped quality. New defect types in ever more complex designs require increased compression. However, increased density of unknown (X) values reduces effective compression. A scan compression method can achieve very high compression and full coverage for any density of unknown values. The described techniques can be fully integrated in the design-for-test (DFT) and automatic test pattern generation (ATPG) flows. Results from using these techniques on industrial designs demonstrate consistent and predictable advantages over other methods.
摘要翻译：扫描测试和扫描压缩是实现成本降低和出货质量的关键。更复杂设计中的新缺陷类型需要增加压缩。然而，未知（X）值的增加的密度降低了有效压缩。扫描压缩方法可以为未知值的任何密度实现非常高的压缩和全覆盖。所描述的技术可以完全集成在测试设计（DFT）和自动测试模式生成（ATPG）流程中。在工业设计中使用这些技术的结果表明与其他方法相比是一致和可预测的优势。

3. 发明申请

US20090271673A1 Dynamically Reconfigurable Shared Scan-In Test Architecture 有权
标题翻译：动态可重配置共享扫描测试架构
公开(公告)号：US20090271673A1
公开(公告)日：2009-10-29
申请号：US12500296
申请日：2009-07-09
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
摘要翻译：提供了低开销动态可重配置的共享扫描测试架构。该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

4. 发明申请

US20080256274A1 Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit 有权
标题翻译：管道附加存储元件，用于移动组合扫描压缩电路的输入/输出数据
公开(公告)号：US20080256274A1
公开(公告)日：2008-10-16
申请号：US11786968
申请日：2007-04-13
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux
IPC分类号： G06F13/38
CPC分类号： G01R31/318547
摘要： An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency.
摘要翻译：电子设备包括基于扫描的电路，其包括组合式解压缩器，组合式压缩器，扫描链和通常包括多个存储元件的逻辑。通常需要通过使用位于外部接口和组合元件之一之间的一个或多个额外的存储元件来将数据移入或移出到电子设备的外部接口的扫描单元之外的周期时间（解压缩机/压缩机）。所述一个或多个附加存储元件形成流水线，其将压缩数据分阶段地跨越外部接口和组合元件之一之间的另外长的路径的小部分。分段移位导致循环时间的限制下降到穿越流水线所需的最长时间。缩短的周期时间又使移位频率相应增加。

5. 发明授权

US07836368B2 Dynamically reconfigurable shared scan-in test architecture 有权
标题翻译：动态可重构共享扫描测试架构
公开(公告)号：US07836368B2
公开(公告)日：2010-11-16
申请号：US12546595
申请日：2009-08-24
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
摘要翻译：提供了低开销动态可重配置的共享扫描测试架构。该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

6. 发明授权

US07836367B2 Dynamically reconfigurable shared scan-in test architecture 有权
公开(公告)号：US07836367B2
公开(公告)日：2010-11-16
申请号：US12539538
申请日：2009-08-11
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

7. 发明申请

US20100083199A1 Increasing Scan Compression By Using X-Chains 有权
标题翻译：通过使用X链增加扫描压缩
公开(公告)号：US20100083199A1
公开(公告)日：2010-04-01
申请号：US12242573
申请日：2008-09-30
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G01R31/318547
摘要： To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
摘要翻译：为了在IC设计测试期间增加扫描压缩，提供X链方法。在该方法中，识别可能捕获X的扫描单元的子集，然后将其放置在单独的X链上。可以提供卸载选择器和/或卸载压缩机的配置和观察模式。配置和观察模式为非-X链提供了大于针对X链提供的第二压缩的第一压缩。可以基于这种配置和观察模式来修改ATPG。这种X链方法可以完全集成在测试（DFT）流程中，不需要额外的用户输入，对面积和时间的影响可以忽略不计。对于具有高X密度的设计，工业设计的测试生成结果显示出显着增加的压缩率，而不损失覆盖范围。

8. 发明授权

US07958472B2 Increasing scan compression by using X-chains 有权
标题翻译：通过使用X链增加扫描压缩
公开(公告)号：US07958472B2
公开(公告)日：2011-06-07
申请号：US12242573
申请日：2008-09-30
申请人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
发明人： Peter Wohl , John A. Waicukauski , Frederic J. Neuveux , Yasunari Kanzawa
IPC分类号： G06F17/50 , G06F11/22 , G01R31/28
CPC分类号： G01R31/318547
摘要： To increase scan compression during testing of an IC design, an X-chain method is provided. In this method, a subset of scan cells that are likely to capture an X are identified and then placed on separate X-chains. A configuration and observation modes for an unload selector and/or an unload compressor can be provided. The configuration and observation modes provide a first compression for non-X-chains that is greater than a second compression provided for X-chains. ATPG can be modified based on such configuration and observation modes. This X-chain method can be fully integrated in the design-for-test (DFT) flow, requires no additional user input, and has negligible impact on area and timing. Test generation results on industrial designs demonstrate significantly increased compression, with no loss of coverage, for designs with high X-densities.
摘要翻译：为了在IC设计测试期间增加扫描压缩，提供X链方法。在该方法中，识别可能捕获X的扫描单元的子集，然后将其放置在单独的X链上。可以提供卸载选择器和/或卸载压缩机的配置和观察模式。配置和观察模式为非-X链提供了大于针对X链提供的第二压缩的第一压缩。可以基于这种配置和观察模式来修改ATPG。这种X链方法可以完全集成在测试（DFT）流程中，不需要额外的用户输入，对面积和时间的影响可以忽略不计。对于具有高X密度的设计，工业设计的测试生成结果显示出显着增加的压缩率，而不损失覆盖范围。

9. 发明授权

US07774663B2 Dynamically reconfigurable shared scan-in test architecture 有权
公开(公告)号：US07774663B2
公开(公告)日：2010-08-10
申请号：US12500296
申请日：2009-07-09
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

10. 发明授权

US07743299B2 Dynamically reconfigurable shared scan-in test architecture 有权
公开(公告)号：US07743299B2
公开(公告)日：2010-06-22
申请号：US12178504
申请日：2008-07-23
申请人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
发明人： Rohit Kapur , Nodari Sitchinava , Samitha Samaranayake , Emil Gizdarski , Frederic J. Neuveux , Suryanarayana Duggirala , Thomas W. Williams
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318536
摘要： A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

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