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1. 发明授权

US07570646B2 Apparatus and method for an interface unit for data transfer between a host processing unit and a multi-target digital signal processing unit in an asynchronous transfer mode 有权
标题翻译：用于以异步传送模式在主处理单元和多目标数字信号处理单元之间进行数据传送的接口单元的装置和方法
公开(公告)号：US07570646B2
公开(公告)日：2009-08-04
申请号：US09964158
申请日：2001-09-26
申请人： Martin Li , Jay B. Reimer , Shakuntala Anjanaiah , Natarajan Seshan , Patrick J. Smith
发明人： Martin Li , Jay B. Reimer , Shakuntala Anjanaiah , Natarajan Seshan , Patrick J. Smith
IPC分类号： H04L12/28
CPC分类号： G06F13/4004 , G06F1/24 , G06F13/28 , G06F13/385
摘要： A slave interface unit controls the exchange of data between a master processing unit and a plurality of slave processing units operating in the asynchronous transfer mode (ATM) of operation. The ATM slave interface unit has a receive unit and a transmit unit that exchange data cells and control signals with the ATM master processing unit. The receive unit and the transmit unit are coupled to a receive buffer storage unit and a transmit buffer storage unit, respectively. The receive buffer storage unit and the transmit buffer storage unit exchange data and control signals with the direct memory access unit. The ATM slave interface unit includes a configuration interface unit having a register that identifies the location in the data cell where the destination address is located and relates the destination address to the particular processing unit or memory location. The receive buffer unit uses the information in the register to determine the destination of the data cell.
摘要翻译：从接口单元控制主处理单元和以异步传送模式（ATM）操作的多个从属处理单元之间的数据交换。 ATM从接口单元具有接收单元和与ATM主处理单元交换数据信元和控制信号的发送单元。接收单元和发送单元分别耦合到接收缓冲存储单元和发送缓冲存储单元。接收缓冲存储单元和发送缓冲存储单元与直接存储器存取单元交换数据和控制信号。 ATM从接口单元包括配置接口单元，其具有标识目的地址所在的数据单元中的位置的寄存器，并将目的地地址与特定处理单元或存储器位置相关联。接收缓冲器单元使用寄存器中的信息来确定数据单元的目的地。

2. 发明申请

US20060256879A1 Rapid I/O Traffic System 有权
标题翻译：快速I / O交通系统
公开(公告)号：US20060256879A1
公开(公告)日：2006-11-16
申请号：US11383330
申请日：2006-05-15
申请人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
发明人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
IPC分类号： H04B14/06
CPC分类号： H04L49/901 , H04L12/18 , H04L49/90 , H04L49/9042
摘要： High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.
摘要翻译： PCI-Express和串行快速I / O等高速网络系统是基于高速串行通信交换网络上的数据包交换。这些数据包头中的信息表示它们所代表的交易类型。在单个队列中排队所有接收到的数据包将导致事务类型之间的交互。可以使用间接方式从共享内存中创建多个独立队列的效果。这提供了有效的集中式分组存储，同时允许对不同事务类型的独立处理。

3. 发明申请

US20060256877A1 Rapid I/O Compliant Message Mapper 审中-公开
标题翻译：快速I / O兼容消息映射器
公开(公告)号：US20060256877A1
公开(公告)日：2006-11-16
申请号：US11383321
申请日：2006-05-15
申请人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
发明人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
IPC分类号： H04B14/06
CPC分类号： G06F13/12
摘要： The Rapid I/O Messaging Logical Layer relies on the receiving device to map the incoming messages into specific memory locations. This uses software programmable mapping registers. The settings are compared to the header fields of the incoming Rapid I/O messages to determine if there is a match, in which case, the packet is mapped to a queue. Accessibility to a queue through the mapping register can be limited to discrete MAILBOX/LETTER combinations, or multiple combinations based on the masking bits. Long messages may be processed through a hardware lookup table implemented to break up transactions into Rapid I/O compliant packets.
摘要翻译：快速I / O消息传递逻辑层依靠接收设备将传入的消息映射到特定的存储位置。这使用软件可编程映射寄存器。将这些设置与传入的快速I / O消息的报头字段进行比较，以确定是否存在匹配，在这种情况下，数据包被映射到队列。通过映射寄存器访问队列的可访问性可以限制为离散MAILBOX / LETTER组合，或者基于掩码位的多个组合。可以通过硬件查找表来处理长消息，以将事务分解成符合快速I / O的数据包。

4. 发明申请

US20060256878A1 Out of Order Message Completion Management 审中-公开
标题翻译：无序消息完成管理
公开(公告)号：US20060256878A1
公开(公告)日：2006-11-16
申请号：US11383322
申请日：2006-05-15
申请人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
发明人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
IPC分类号： H04B14/06
CPC分类号： G06F13/42
摘要： A packet transmission system based on a simple linear linked list of packet descriptors is difficult to implement with modern switch based system because transmission acknowledgments may occur out of order in relation to packet transmission. The problem lies in how packet completion is indicated to the CPU to enable for efficient packet processing. A scoreboard system is scalable to support multiple single-segment messages and multiple multi-segment messages for hundreds of packets. When a message/segment has been sent out, the context information for the packet is remembered and its key is indexed into a CAM. When segment/message response comes back, a simple hardware lookup is performed, and the associated context information is retrieved.
摘要翻译：基于分组描述符的简单线性链表的分组传输系统难以用现代交换机系统实现，因为传输确认可能与分组传输有关。问题在于如何向CPU指示数据包的完成情况，以便能够进行有效的数据包处理。记分板系统是可扩展的，以支持数百个数据包的多个单段消息和多个多段消息。当消息/段已经发送出去时，会记住数据包的上下文信息，并将其密钥索引到CAM中。当段/消息响应回来时，执行简单的硬件查找，并且检索相关联的上下文信息。

5. 发明申请

US20060256876A1 Fast Decode of Pending Interrupts 审中-公开
标题翻译：快速解码等待中断
公开(公告)号：US20060256876A1
公开(公告)日：2006-11-16
申请号：US11383317
申请日：2006-05-15
申请人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
发明人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
IPC分类号： H04B14/06
CPC分类号： G06F13/12
摘要： This invention enables many interrupt source bits spread among multiple interrupt registers. An interrupt status decode register reduces the number of read cycles required to decode the interrupt source. Each unique interrupt source has a predefined and fixed logical mapping to each bit of the decode register. The logical mapping is flexible per application. The decode register bit is set if the interrupt source is asserted and the interrupt source is mapped to that particular physical interrupt. Since each physical interrupt has an associated decode register, the ability to orthogonally arrange the sources and reduce the number of register reads is even greater.
摘要翻译：本发明使许多中断源位在多个中断寄存器之间扩展。中断状态解码寄存器减少了解码中断源所需的读周期数。每个独特的中断源具有对解码寄存器的每个位的预定义和固定的逻辑映射。每个应用程序的逻辑映射是灵活的。如果中断源被置位且中断源映射到该特定物理中断，则解码寄存器位置1。由于每个物理中断都具有相关的解码寄存器，所以能够正确排列源并减少寄存器读取的数量甚至更大。

6. 发明申请

US20050065212A1 Use of at least one 10-hydroxy-2-decenoic acid derivative in compositions for treating the cuteous signs of aging 审中-公开
标题翻译：在组合物中使用至少一种10-羟基-2-癸烯酸衍生物来治疗老化迹象
公开(公告)号：US20050065212A1
公开(公告)日：2005-03-24
申请号：US10480502
申请日：2002-06-14
申请人： Nathalie Pineau , Dominique Fagot , Emile Benechie , Martin Li , Francoise Picot , Pierre Potier
发明人： Nathalie Pineau , Dominique Fagot , Emile Benechie , Martin Li , Francoise Picot , Pierre Potier
IPC分类号： A61K8/00 , A61K8/02 , A61K8/06 , A61K8/30 , A61K8/37 , A61K8/41 , A61K31/22 , A61K31/225 , A61K31/231 , A61P17/16 , A61P43/00 , A61Q19/00
CPC分类号： A61Q19/00 , A61K8/37 , A61Q19/08
摘要： The present invention relates to a method of inhibiting degradation of skin or mucous membranes by inhibiting action of collagenases comprising applying to the skin or mucous membranes a composition comprising at least one of 10-hydroxy-2-decenoic acid derivative. The invention also relates to a process for treating signs of aging.
摘要翻译：本发明涉及通过抑制胶原酶的作用来抑制皮肤或粘膜的降解的方法，包括向皮肤或粘膜施用包含10-羟基-2-癸烯酸衍生物中的至少一种的组合物。本发明还涉及一种治疗老化迹象的方法。

7. 发明申请

US20060268714A1 Rapid I/O Compliant Congestion Control 审中-公开
标题翻译：快速I / O兼容拥塞控制
公开(公告)号：US20060268714A1
公开(公告)日：2006-11-30
申请号：US11383316
申请日：2006-05-15
申请人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
发明人： Andre Szczepanek , Martin Li , Steven Marshall , Travis Scheckel
IPC分类号： H04J1/16
CPC分类号： G01R31/31858 , H04L7/0041 , H04L7/0331 , H04L47/10 , H04L47/12 , H04L47/2441 , H04L47/266 , H04L47/41 , H04L49/90 , Y02D50/30
摘要： The management of flows can be simplified by only keeping unique flow information for locally important flows, and aggregating all other flows together. A flow control table of 16 entries, 15 unique and 1 aggregate is usually sufficient, particularly in systems where the traffic flows are relatively static. This greatly reduces the required logic for Xoff/Xon counters and timeout monitors Rather than every packet source checking each packet it sends, the flows needed by each unit are registered in the flow table and the table logic indicates to each unit whether it has any blocked flows.
摘要翻译：流量的管理可以通过仅保留本地重要流量的独特流量信息，并将所有其他流量汇总在一起来简化。 16个条目，15个唯一和1个聚合的流量控制表通常是足够的，特别是在流量相对静态的系统中。这大大减少了Xoff / Xon计数器和超时监视器所需的逻辑，而不是每个数据包源检查每个数据包发送的数据包，每个单元所需的流量都会记录在流程表中，表逻辑表明每个单元是否有任何阻塞流动。

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