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1. 发明授权

US06405273B1 Data processing device with memory coupling unit 有权
标题翻译：具有存储器耦合单元的数据处理设备
公开(公告)号：US06405273B1
公开(公告)日：2002-06-11
申请号：US09192170
申请日：1998-11-13
申请人： Rod G. Fleck , Klaus Oberlaender , Gigy Baror , Alfred Eder , Le Trong Nguyen
发明人： Rod G. Fleck , Klaus Oberlaender , Gigy Baror , Alfred Eder , Le Trong Nguyen
IPC分类号： G06F1300
CPC分类号： G06F13/1678
摘要： A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The coupling unit comprises a bus having a bus width of at least 2n-bits forming at least a first and second sub-bus, first couplers for coupling each memory bank or the register file selectively with one of the sub-busses, and second couplers for coupling the register file or the memory banks with the bus.
摘要翻译：公开了具有多个寄存器的寄存器文件的数据处理单元。提供具有多个n位输入/输出端口的存储器，以及用于将存储器与寄存器文件耦合的耦合单元，用于寻址存储体的存储器地址和选择单元。耦合单元包括具有形成至少第一和第二子总线的至少2n位的总线宽度的总线，用于将每个存储体或寄存器文件选择性地耦合到子总线之一的第一耦合器和第二耦合器用于将寄存器文件或存储体与总线耦合。

2. 发明授权

US06507899B1 Interface for a memory unit 有权
标题翻译：存储单元的接口
公开(公告)号：US06507899B1
公开(公告)日：2003-01-14
申请号：US09460534
申请日：1999-12-13
申请人： Klaus Oberlaender , Sabeen Randhawa , Yannick Martelloni , Manfred Henftling , Rami Zemach , Zohar Peleg , Christian Wiedholz , Gigy Baror , Doron Shoham , Oded Trainin , Niv Margalit
发明人： Klaus Oberlaender , Sabeen Randhawa , Yannick Martelloni , Manfred Henftling , Rami Zemach , Zohar Peleg , Christian Wiedholz , Gigy Baror , Doron Shoham , Oded Trainin , Niv Margalit
IPC分类号： G06F1208
CPC分类号： G06F12/0215
摘要： An interface circuit for coupling a data handling unit with a memory unit having control inputs, an address signal input, a data signal input, and a data signal output is described. The interface circuit comprises an address buffer having an input and an output, said input receiving an address signal from said data handling unit, a first multiplexer which couples said memory unit with either said output of said address buffer or with said address signal, a data buffer having an input and an output, said input receiving a data signal from said data handling unit and said output being coupled with said memory data input, a second multiplexer for selecting either said memory data signal output or said data buffer output, and a comparator for comparing said address signal with the signal from said address buffer output, generating a control signal which controls said second multiplexer.
摘要翻译：描述了一种用于将数据处理单元与具有控制输入，地址信号输入，数据信号输入和数据信号输出的存储单元耦合的接口电路。接口电路包括具有输入和输出的地址缓冲器，所述输入接收来自所述数据处理单元的地址信号，第一多路复用器将所述存储单元与所述地址缓冲器的所述输出或所述地址信号相耦合，数据具有输入和输出的缓冲器，所述输入接收来自所述数据处理单元的数据信号，并且所述输出与所述存储器数据输入耦合;第二多路复用器，用于选择所述存储器数据信号输出或所述数据缓冲器输出;以及比较器用于将所述地址信号与来自所述地址缓冲器输出的信号进行比较，产生控制所述第二多路复用器的控制信号。

3. 发明授权

US06256253B1 Memory device with support for unaligned access 有权
标题翻译：支持未对齐访问的内存设备
公开(公告)号：US06256253B1
公开(公告)日：2001-07-03
申请号：US09507568
申请日：2000-02-18
申请人： Klaus Oberlaender , Sabeen Randhawa , Vincent Rez{haeck over (a)}rd , Rod G. Fleck
发明人： Klaus Oberlaender , Sabeen Randhawa , Vincent Rez{haeck over (a)}rd , Rod G. Fleck
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/10 , G11C8/12
摘要： An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.
摘要翻译：集成存储器包括多个数据线和与每个数据线相关联的多个解码器。每个数据线可以寻址单个存储器单元或多个存储器单元。此外，每个数据线可以是存储器的字线或位线。每个解码器在接收到其相关联的地址信号时产生使能信号。提供具有两个输入和与每条数据线相关联的输出的多路复用器。每个解码器的使能信号被提供给相关联的多路复用器的第一输入和与下一较高寻址数据线相关联的复用器的第二输入，以及用于控制所述多路复用器的控制输入。

4. 发明授权

US06512716B2 Memory device with support for unaligned access 有权
标题翻译：支持未对齐访问的内存设备
公开(公告)号：US06512716B2
公开(公告)日：2003-01-28
申请号：US09772497
申请日：2001-01-29
申请人： Klaus Oberlaender , Sabeen Randhawa , Vincent Rez{haeck over (a)}rd , Rod G. Fleck
发明人： Klaus Oberlaender , Sabeen Randhawa , Vincent Rez{haeck over (a)}rd , Rod G. Fleck
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C8/10 , G11C8/12
摘要： An integrated memory comprises a plurality of data lines and a plurality of decoders being associated to each data line. Each data line can address a single memory cell or a plurality of memory cells. Also, each data line can be either a word line or a bit line of a memory. Each decoder generates an enable signal upon receiving of its associated address signal. A plurality of multiplexers having two inputs and an output associated to each data line are provided. The enable signal of each decoder is supplied to a first input of the associated multiplexer and to a second input of the multiplexer associated to the next higher addressed data line, and a control input for controlling said multiplexers.
摘要翻译：集成存储器包括多个数据线和与每个数据线相关联的多个解码器。每个数据线可以寻址单个存储器单元或多个存储器单元。此外，每个数据线可以是存储器的字线或位线。每个解码器在接收到其相关联的地址信号时产生使能信号。提供具有两个输入和与每条数据线相关联的输出的多路复用器。每个解码器的使能信号被提供给相关联的多路复用器的第一输入和与下一较高寻址数据线相关联的复用器的第二输入，以及用于控制所述多路复用器的控制输入。

5. 发明申请

US20120030531A1 Safe Memory Storage By Internal Operation Verification 有权
标题翻译：通过内部操作验证安全内存存储
公开(公告)号：US20120030531A1
公开(公告)日：2012-02-02
申请号：US12847450
申请日：2010-07-30
申请人： Simon Brewerton , Neil Hastie , Paul Hubbert , Klaus Oberlaender , Robert Wiesner , Antonio Vilela , Alfred Eder
发明人： Simon Brewerton , Neil Hastie , Paul Hubbert , Klaus Oberlaender , Robert Wiesner , Antonio Vilela , Alfred Eder
IPC分类号： G11C29/04 , G06F11/22 , G11C8/10
CPC分类号： G11C29/44 , G11C29/024 , G11C29/025 , G11C2029/0411
摘要： The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.
摘要翻译：所公开的发明提供了用于检测地址线（例如，字线，位线）存储器故障的结构和方法。在一个实施例中，该方法和结构包括通过从存储器阵列内部的激活元件（例如，字线）重新编码内部产生的地址信号来生成地址签名。再生地址签名可以与请求的存储器地址位置进行比较。如果再生地址签名和存储器位置等于存储器阵列中没有错误，但是如果再生地址签名和存储器位置等于存储器阵列中存在错误。因此，对地址签名的重新编码提供闭环检查，即在存储器阵列中实际激活的字线和/或位线是正确请求的字线和/或位线，没有其他字线或位线也被触发，字线和/或位线是连续的。

6. 发明授权

US08560899B2 Safe memory storage by internal operation verification 有权
标题翻译：通过内部操作验证安全内存存储
公开(公告)号：US08560899B2
公开(公告)日：2013-10-15
申请号：US12847450
申请日：2010-07-30
申请人： Simon Brewerton , Neil Hastie , Paul Hubbert , Klaus Oberlaender , Robert Wiesner , Antonio Vilela , Alfred Eder , Glenn Ashley Farrall
发明人： Simon Brewerton , Neil Hastie , Paul Hubbert , Klaus Oberlaender , Robert Wiesner , Antonio Vilela , Alfred Eder , Glenn Ashley Farrall
IPC分类号： G06F11/00
CPC分类号： G11C29/44 , G11C29/024 , G11C29/025 , G11C2029/0411
摘要： The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.
摘要翻译：所公开的发明提供了用于检测地址线（例如，字线，位线）存储器故障的结构和方法。在一个实施例中，该方法和结构包括通过从存储器阵列内部的激活元件（例如，字线）重新编码内部产生的地址信号来生成地址签名。再生地址签名可以与请求的存储器地址位置进行比较。如果再生地址签名和存储器位置等于存储器阵列中没有错误，但是如果再生地址签名和存储器位置等于存储器阵列中存在错误。因此，对地址签名的重新编码提供闭环检查，即在存储器阵列中实际激活的字线和/或位线是正确请求的字线和/或位线，没有其他字线或位线也被触发，字线和/或位线是连续的。

7. 发明申请

US20110231718A1 MEMORY REPAIR 有权
标题翻译：记忆修复
公开(公告)号：US20110231718A1
公开(公告)日：2011-09-22
申请号：US13151661
申请日：2011-06-02
申请人： Klaus Oberlaender
发明人： Klaus Oberlaender
IPC分类号： G11C29/08 , G06F11/27
CPC分类号： G11C29/52 , G11C11/41 , G11C29/44 , G11C29/4401 , G11C2029/0409
摘要： A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.
摘要翻译：一种具有存储器的存储器芯片，具有多个非冗余存储器线路和多个冗余存储器线路，以及控制器，被配置为在运行时间期间将冗余存储器线路分配给故障存储器线路。

8. 发明申请

US20050102572A1 Memory debugger for system-on-a-chip designs 有权
标题翻译：用于片上系统设计的内存调试器
公开(公告)号：US20050102572A1
公开(公告)日：2005-05-12
申请号：US10705101
申请日：2003-11-10
申请人： Klaus Oberlaender
发明人： Klaus Oberlaender
IPC分类号： G06F11/00 , G06F17/50
CPC分类号： G06F17/5022
摘要： A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal transaction records are generated for each incremental memory access (e.g., data write operations). Each transaction record includes a timestamp, address and data values. The transaction record information is stored/captured on a high level-based (i.e., system address-based) domain that takes into account all the tiling, interleaving, scrambling, and unaligned accessing used in the simulated SOC design, rather than on a low level-based (i.e., physical memory address-based) domain. Upon completing the simulation, the instantaneous memory contents at any selected point in time during the simulated execution are calculated by combining the initial data and intermediate transaction record information. Automatic memory dump and sanity check tests verify the integrity of the final data value and incremental transactions. Cache memory information is collected and displayed using a system-level format.
摘要翻译：一种利用加载到仿真模型中的初始存储器值的SOC设计的仿真/调试方法。然后执行测试程序，并且为每个增量存储器访问（例如，数据写入操作）生成递增交易记录。每个事务记录都包含时间戳，地址和数据值。交易记录信息被存储/捕获在考虑到模拟SOC设计中使用的所有平铺，交织，加扰和非对准访问的高级（即，基于系统地址的）域上，而不是低（即基于物理内存地址的）域。在完成仿真之后，通过组合初始数据和中间交易记录信息来计算模拟执行期间任何选定时间点的瞬时存储器内容。自动内存转储和完整性检查测试验证最终数据值和增量事务的完整性。使用系统级格式收集和显示缓存内存信息。

9. 发明授权

US06872446B2 White, biaxially oriented film made from a crystallizable thermoplastic with high whiteness and with additional functionality 有权
标题翻译：由具有高白度和附加功能的可结晶热塑性塑料制成的白色双轴取向薄膜
公开(公告)号：US06872446B2
公开(公告)日：2005-03-29
申请号：US10084028
申请日：2002-02-27
申请人： Ursula Murschall , Ulrich Kern , Klaus Oberlaender , Thorsten Kiehne
发明人： Ursula Murschall , Ulrich Kern , Klaus Oberlaender , Thorsten Kiehne
IPC分类号： B32B27/20 , B29C55/12 , B29K101/12 , B29K105/16 , C08J5/18 , B32B3/26
CPC分类号： C08J5/18 , C08J2367/02 , C08K3/22 , C08K5/0041 , C08K2003/2241 , Y10S428/91 , Y10T428/249953 , Y10T428/249958 , Y10T428/31786 , C08L67/02
摘要： The invention relates to a white, biaxially oriented film made from a crystallizable thermoplastic with high whiteness, the thickness of the film being in the range from 10 to 500 μm. The film comprises at least one rutile-type titanium dioxide as pigment and an optical brightener, with or without other additives, and has at least one additional functionality. The expression “additional functionality” includes UV resistance, yellowing resistance, photooxidative stability, flame retardancy, and sealability. This film may have one or more of the functional properties. All of these films are capable of cost-effective thermoforming, have good orientability, and have very good optical and mechanical properties. The invention further relates to a process for its production.
摘要翻译：本发明涉及一种由具有高白度的可结晶热塑性塑料制成的白色双轴取向薄膜，该薄膜的厚度在10-500μm的范围内。该膜包含至少一种作为颜料的金红石型二氧化钛和具有或不具有其它添加剂的荧光增白剂，并具有至少一种附加功能。表述“附加功能”包括耐紫外线性，耐黄变性，光氧化稳定性，阻燃性和密封性。该膜可以具有一种或多种功能性质。所有这些膜都能够具有成本效益的热成型，具有良好的取向性，并且具有非常好的光学和机械性能。本发明还涉及其生产方法。

10. 发明授权

US06855435B2 Transparent, UV-stabilized film made from a crystallizable thermoplastic 有权
标题翻译：由可结晶热塑性塑料制成的透明UV稳定膜
公开(公告)号：US06855435B2
公开(公告)日：2005-02-15
申请号：US10428066
申请日：2003-05-02
申请人： Ursula Murschall , Guenther Crass , Guenter Bewer , Klaus Oberlaender
发明人： Ursula Murschall , Guenther Crass , Guenter Bewer , Klaus Oberlaender
IPC分类号： C08J3/22 , B29C55/12 , B32B27/18 , B32B27/36 , C08J5/18 , C08K5/03 , C08K5/10 , C08K5/1539 , C08K5/1545 , C08K5/3475 , C08K5/3492 , C08K5/353 , C08L67/02 , C08L101/00 , C09K3/00 , B32B27/08 , B32B31/30
CPC分类号： C08K5/353 , B32B27/36 , C08J5/18 , C08J2367/02 , C08K5/10 , C08K5/1545 , C08K5/3475 , C08K5/3492 , Y10S428/91 , Y10T428/31786 , Y10T428/31855
摘要： A transparent film whose thickness is in the range from 1 to 500 μm and which comprises, as principal constituent, a crystallizable thermoplastic, wherein the film comprises at least one UV stabilizer as light stabilizer and at least one optical brightener, and to the use of the film, and also to a process for its production.
摘要翻译：一种透明膜，其厚度在1至500μm的范围内，并且其以可结晶热塑性材料为主要成分，其中该膜包含至少一种作为光稳定剂的UV稳定剂和至少一种荧光增白剂，以及使用电影，也是一个生产过程。

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