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    • 1. 发明授权
    • Delta-sigma D/A converter
    • Delta-sigma D / A转换器
    • US08988261B2
    • 2015-03-24
    • US13884639
    • 2011-10-20
    • Roberto LugliMichael KornAlfred ZotzStephan Damith
    • Roberto LugliMichael KornAlfred ZotzStephan Damith
    • H03M1/82H03M3/02H03M3/00H03M7/30
    • H03M3/02H03M3/358H03M3/506H03M7/3028
    • A delta-sigma D/A converter, by which a digital valued, input signal is convertible into a binary, clock signal time discrete, output signal. By forming an average value of the output signal over a number of clock signal cycles, an analog value of the input signal can be displayed. The delta-sigma D/A converter is embodied in such a manner that, in use, it provides the output signal by serial arrangement of signal patterns of a set of signal patterns, wherein the signal patterns of the set are, in each case, binary, clock signal time discrete and extend over a signal pattern cycles total of a plurality of clock cycles. At least two signal patterns of the set have mutually different signal pattern average values, which are formed over the respective signal pattern cycles total, and all signal patterns of the set have, in each case, essentially the same number, especially exactly the same number, of edges.
    • Δ-ΣD / A转换器,数字值的输入信号可转换为二进制时钟信号时间离散的输出信号。 通过在多个时钟信号周期上形成输出信号的平均值,可以显示输入信号的模拟值。 Δ-ΣD / A转换器以这样的方式实现:在使用中,其通过串联布置一组信号模式的信号模式来提供输出信号,其中在每种情况下,该组信号模式, 二进制,时钟信号时间离散并在信号模式上延伸总共多个时钟周期。 该集合的至少两个信号模式具有相互不同的信号模式平均值,它们在相应的信号模式周期总数上形成,并且在每种情况下,该集合的所有信号模式具有基本上相同的数量,特别是完全相同的数量 ,边缘。
    • 2. 发明申请
    • Delta-Sigma D/A Converter
    • Delta-Sigma D / A转换器
    • US20130234872A1
    • 2013-09-12
    • US13884639
    • 2011-10-20
    • Roberto LugliMichael KornAlfred ZotzStephan Damith
    • Roberto LugliMichael KornAlfred ZotzStephan Damith
    • H03M3/02
    • H03M3/02H03M3/358H03M3/506H03M7/3028
    • A delta-sigma D/A converter, by which a digital valued, input signal is convertible into a binary, clock signal time discrete, output signal. By forming an average value of the output signal over a number of clock signal cycles, an analog value of the input signal can be displayed. The delta-sigma D/A converter is embodied in such a manner that, in use, it provides the output signal by serial arrangement of signal patterns of a set of signal patterns, wherein the signal patterns of the set are, in each case, binary, clock signal time discrete and extend over a signal pattern cycles total of a plurality of clock cycles. At least two signal patterns of the set have mutually different signal pattern average values, which are formed over the respective signal pattern cycles total, and all signal patterns of the set have, in each case, essentially the same number, especially exactly the same number, of edges.
    • Δ-ΣD / A转换器,数字值的输入信号可转换为二进制时钟信号时间离散的输出信号。 通过在多个时钟信号周期上形成输出信号的平均值,可以显示输入信号的模拟值。 Δ-ΣD / A转换器以这样的方式实现:在使用中,它通过串联布置一组信号图案的信号图案来提供输出信号,其中在每种情况下,该组的信号图案, 二进制,时钟信号时间离散并在信号模式上延伸总共多个时钟周期。 该集合的至少两个信号模式具有相互不同的信号模式平均值,它们在相应的信号模式周期总数上形成,并且在每种情况下,该集合的所有信号模式具有基本上相同的数量,特别是完全相同的数量 ,边缘。