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1. 发明授权

US5972769A Self-aligned multiple crown storage capacitor and method of formation 失效
标题翻译：自对准多冠储能电容器及其形成方法
公开(公告)号：US5972769A
公开(公告)日：1999-10-26
申请号：US993637
申请日：1997-12-18
申请人： Robert Yung-Hsi Tsu , Jing Shu , Isamu Asano , Jeffrey Alan McKee
发明人： Robert Yung-Hsi Tsu , Jing Shu , Isamu Asano , Jeffrey Alan McKee
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A self-aligned multiple crown storage cell structure 10 for use in a semiconductor memory device and method of formation that provide a storage capacitor with increased capacitance. A double crown storage cell structure embodiment 10 can be formed by patterning a contact via 18 into a planarized base layer that can include an insulating layer 12, an etch stop layer 14, and a hard mask layer 16, depositing a first conductive layer 20, etching the first conductive layer 20, etching the hard mask layer 16, depositing a second conductive layer 24 onto the conductive material-coated patterned via 18 and the etch stop layer 14, depositing a sacrificial (oxide) layer 26 onto the second conductive layer 24, etching the sacrificial layer 26, depositing a third conductive layer 28, and etching conductive material and the remaining sacrificial layer 26. The last several steps can be repeated to form a storage cell structure 10 with three or more crowns.
摘要翻译：一种用于半导体存储器件的自对准多冠形存储单元结构10以及提供具有增加的电容的存储电容器的形成方法。可以通过将接触通孔18图案化成可以包括绝缘层12，蚀刻停止层14和硬掩模层16，沉积第一导电层20的平坦化基底层来形成双冠形存储单元结构实施例10，蚀刻第一导电层20，蚀刻硬掩模层16，将第二导电层24沉积到涂覆有导电材料的图案化通孔18和蚀刻停止层14上，在第二导电层24上沉积牺牲（氧化物）层26 蚀刻牺牲层26，沉积第三导电层28，蚀刻导电材料和剩余的牺牲层26.最后几个步骤可以重复以形成具有三个或更多个冠的存储单元结构10。

2. 发明授权

US5909628A Reducing non-uniformity in a refill layer thickness for a semiconductor device 失效
标题翻译：降低半导体器件的再填充层厚度的不均匀性
公开(公告)号：US5909628A
公开(公告)日：1999-06-01
申请号：US804484
申请日：1997-02-21
申请人： Amitava Chatterjee , Theodore W. Houston , Ih-Chin Chen , Agerico L. Esquirel , Somnath Nag , Iqbal Ali , Keith A. Joyner , Yin Hu , Jeffrey Alan McKee , Peter Stewart McAnally
发明人： Amitava Chatterjee , Theodore W. Houston , Ih-Chin Chen , Agerico L. Esquirel , Somnath Nag , Iqbal Ali , Keith A. Joyner , Yin Hu , Jeffrey Alan McKee , Peter Stewart McAnally
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3105 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.
摘要翻译：制造半导体器件或集成电路的技术产生平坦化的补充层，其在抛光之后具有比较均匀的厚度，例如通过化学机械抛光（CMP）。在通常由场氧化物占据的衬底的该部分中的有源区域之间插入虚拟有源区，以便在这些区域中减少在CMP期间发生的“凹陷”。虚拟有源区域可以采取大块，部分或完全形成的环形结构的形状，或者可以调节其面积密度以匹配衬底的该区域中的有源区的面积密度的多个柱。支柱的设计规则可以是在多晶硅线或第一级金属化线被放置以避免寄生电容的地方放置柱子。

3. 发明授权

US6136700A Method for enhancing the performance of a contact 失效
标题翻译：提高接触性能的方法
公开(公告)号：US6136700A
公开(公告)日：2000-10-24
申请号：US992268
申请日：1997-12-17
申请人： Peter S. McAnally , Jeffrey Alan McKee , Dirk Noel Anderson
发明人： Peter S. McAnally , Jeffrey Alan McKee , Dirk Noel Anderson
IPC分类号： H01L23/522 , H01L21/306 , H01L21/31 , H01L21/316 , H01L21/60 , H01L21/768 , H01L23/31 , H01L23/485 , H01L21/44
CPC分类号： H01L21/76897 , H01L23/3171 , H01L23/485 , H01L2924/0002 , H01L2924/12044 , H01L2924/19041 , Y10S257/90
摘要： A self-aligned contact (122) to a substrate (12) of a semiconductor device (100) is formed using a stopping layer (110) overlying the substrate (12). The stopping layer (110) comprising a material selected from the group consisting of silicon-rich nitride, silicon-rich oxide, carbon-rich nitride, silicon carbide, boron nitride, organic spin-on-glass, graphite, diamond, carbon-rich oxide, nitrided oxide, and organic polymer. The stopping layer (110) promotes better semiconductor device (100) performance by contributing to greater selectivity with respect to an etch process used to remove an insulating layer (112) formed overlying the stopping layer (110).
摘要翻译：使用覆盖在基板（12）上的停止层（110），形成与半导体器件（100）的基板（12）的自对准接触（122）。阻挡层（110）包括选自富硅氮化物，富硅氧化物，富碳氮化物，碳化硅，氮化硼，有机旋涂玻璃，石墨，金刚石，富碳的材料氧化物，氮化氧化物和有机聚合物。阻挡层（110）通过有助于相对于用于去除形成在阻挡层（110）上的绝缘层（112）的蚀刻工艺的更大的选择性来促进更好的半导体器件（100）性能。

4. 发明授权

US5804088A Intermediate layer lithography 失效
公开(公告)号：US5804088A
公开(公告)日：1998-09-08
申请号：US679041
申请日：1996-07-12
申请人： Jeffrey Alan McKee
发明人： Jeffrey Alan McKee
IPC分类号： G03F7/09 , H01L21/027 , G03C5/00
CPC分类号： G03F7/091 , H01L21/0276
摘要： An isotropic or partially isotropic etch shrinks lithographically patterned photoresist (211, 212) to yield reduced linewidth patterned photoresist (213, 214) with a buried antireflective coating also acting as an etchstop or a sacrificial layer. The reduced linewidth pattern (213, 214) provide an etch mask for subsequent anisotropic etching of underlying material such as polysilicon (206) or metal or insulator or ferroelectric.

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