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    • 1. 发明申请
      US20090246083A1 TIMING BASED METHOD AND APPARATUS FOR MONITORING DRINKING WATER PURITY AND ENCOURAGING ROUTINE TESTING OF DRINKING WATER PURITY 审中-公开
    • TIMING BASED METHOD AND APPARATUS FOR MONITORING DRINKING WATER PURITY AND ENCOURAGING ROUTINE TESTING OF DRINKING WATER PURITY
    • 基于时间的方法和装置，用于监测饮用水的纯度和饮用水的纯度测试
    • US20090246083A1
    • 2009-10-01
    • US12055198
    • 2008-03-25
    • Robert Samborn , Charles F. Lee , Jin H. Lee , Yun-Ho Son
    • Robert Samborn , Charles F. Lee , Jin H. Lee , Yun-Ho Son
    • G01N27/00 , G04F10/00
    • G01N27/06
    • An invention is provided for encouraging routine testing for TDS levels in a liquid. The invention includes a conductivity sensor capable of sensing a conductivity level of a liquid, and a processor in electrical communication with the conductivity sensor. The processor has logic that calculates a TDS level for the liquid based on the conductivity level of the liquid. The calculated TDS level for the liquid is then displayed on a display in electrical communication with the processor. Also included is a speaker, which is electrical communication with the processor. To provide automatic reminders to the user, an integrated timing mechanism is included that is in communication with the processor. When a predetermined period of time has elapsed, such as the period of time between periodic TDS level testing, the integrated timing mechanism sends a signal to the processor to provide an alert to the user to test the TDS level.
    • 提供了一种用于鼓励液体中TDS水平的常规测试的发明。 本发明包括能够感测液体的导电率的电导率传感器和与电导率传感器电连通的处理器。 处理器具有基于液体的电导率水平计算液体的TDS水平的逻辑。 然后将所计算的液体TDS水平显示在与处理器电气通信的显示器上。 还包括一个扬声器，它与处理器进行电气通信。 为了向用户提供自动提醒，包括与处理器通信的集成定时机制。 当经过预定时间段（例如周期性TDS电平测试之间的时间段）时，集成定时机制向处理器发送信号以向用户提供警报以测试TDS电平。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US5236858A Method of manufacturing a semiconductor device with vertically stacked structure 失效
    • Method of manufacturing a semiconductor device with vertically stacked structure
    • 制造具有垂直堆叠结构的半导体器件的方法
    • US5236858A
    • 1993-08-17
    • US796845
    • 1991-11-25
    • Kyu H. Lee , Sang H. Chai , Soon I. Yeo , Jin S. Kim , Jin H. Lee
    • Kyu H. Lee , Sang H. Chai , Soon I. Yeo , Jin S. Kim , Jin H. Lee
    • H01L27/10 , H01L21/337 , H01L21/762 , H01L21/8242 , H01L27/108 , H01L29/808
    • H01L27/10864 , H01L21/76235 , H01L27/10841
    • The invention relates to a method of manufacturing a DRAM in which a storage capacitor is stacked vertically over a switching junction FET. There is provided a method comprising the steps of: (a) sequentially depositing a nitride layer and a first oxide layer on a substrate; (b) etching away the oxide and nitride layer by means of a trench mask so as to define field and active regions; (c) etching away the substrate of the field region up to a predetermined depth using the remaining oxide and nitride layers as a mask so as to form trench portion; (d) forming a first spacer at the edges of the trench portion; (e) further etching away the substrate of the field region up to a predetermined depth using the remaining oxide and nitride layers and the first spacer as a mask; (f) forming a second spacer at edges of the trench portion; (g) growing a device isolating field oxide layer of the field region after etching away the substrate of the field region; (h) depositing a polysilicon layer thereon after removal of the second spacer and implanting impurity into the substrate through the polysilicon layer so as to form a gate junction region; (i) etching away the polysilicon layer only on the field region so as to define a word line; (j) growing an insulating layer in the field region and removing the first oxide layer on the nitride layer; (k) flatting projected portions of the polysilicon layer and forming an oxide layer on the projected portion and the insulating layer so as to self-contact between storage node of the storage capacitor and drain of the junction FET; (I) depositing a patterned polysilicon layer for the storage node thereon and forming a capacitor dielectric layer around the patterned polysilicon layer; and (m) depositing a polysilicon layer for a plate electrode and defining a bit line by means of a bit line mask.
    • 本发明涉及一种制造其中存储电容器垂直堆叠在开关结FET上的DRAM的方法。 提供了一种方法，包括以下步骤：（a）在衬底上依次沉积氮化物层和第一氧化物层; （b）通过沟槽掩模蚀刻掉氧化物和氮化物层，以便限定场和有源区; （c）使用剩余的氧化物和氮化物层作为掩模将场区的衬底刻蚀至预定的深度，以形成沟槽部分; （d）在沟槽部分的边缘处形成第一间隔物; （e）使用剩余的氧化物和氮化物层和第一间隔物作为掩模，进一步蚀刻掉场区的衬底达预定深度; （f）在沟槽部分的边缘处形成第二间隔物; （g）在蚀刻掉场区的衬底之后，生长场隔离场区氧化层的器件; （h）在去除所述第二间隔物之后在其上沉积多晶硅层并通过所述多晶硅层将杂质注入所述衬底中以形成栅极结区域; （i）仅在场区域上蚀刻去除多晶硅层，以便限定字线; （j）在场区域中生长绝缘层并去除氮化物层上的第一氧化物层; （k）使所述多晶硅层的突出部分平坦化并在所述突出部分和所述绝缘层上形成氧化物层，以便在所述存储电容器的存储节点与所述结型FET的漏极之间自我接触; （I）在其上沉积用于存储节点的图案化多晶硅层并在图案化多晶硅层周围形成电容器介电层; 和（m）沉积用于平板电极的多晶硅层并借助位线掩模限定位线。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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