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1. 发明授权

US06535041B1 Strobe circuit keeper arrangement providing reduced power consumption 失效
标题翻译：频闪电路保持器布置提供降低的功耗
公开(公告)号：US06535041B1
公开(公告)日：2003-03-18
申请号：US10093440
申请日：2002-03-07
申请人： Robert John Bucki , Sang Hoo Dhong , Jeffrey Herbert Fischer , Joel Abraham Silberman , Osamu Takahashi
发明人： Robert John Bucki , Sang Hoo Dhong , Jeffrey Herbert Fischer , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： H03K312
CPC分类号： H03K3/356113 , H03K3/012 , H03K3/013
摘要： A dynamic node keeper device for a dynamic strobe circuit is controlled by the signal at the intermediate node, that is, the signal at the output of the strobe component. By controlling the dynamic node keeper device through the strobe component output, the keeper device is active or conductive only when necessary to protect against noises in the pull down network for the strobe circuit. At all other times in the course of operation of the dynamic strobe circuit, the dynamic node keeper device according to the invention is nonconductive or inactive. Thus, the dynamic strobe circuit according to the invention reduces power consumption.
摘要翻译：用于动态选通电路的动态节点保持器装置由中间节点处的信号，即选通组件输出端的信号控制。通过通过选通分量输出来控制动态节点保持器装置，只有在必要时保持装置才有效或不导通，以防止用于选通电路的下拉网络中的噪声。在动态频闪电路的操作过程中的所有其他时间，根据本发明的动态节点保持装置是不导通或不活动的。因此，根据本发明的动态选通电路降低功耗。

2. 发明授权

US07225422B2 Wire trimmed programmable logic array 有权
标题翻译：电线修剪可编程逻辑阵列
公开(公告)号：US07225422B2
公开(公告)日：2007-05-29
申请号：US10464879
申请日：2003-06-19
申请人： Robert John Bucki , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Robert John Bucki , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of designing a logic circuit includes providing a leaf cell having at least one transistor. The leaf is suitable for use as a 1-cell or a 0-cell in the logic circuit. A first array of abutting leaf cells is tiled using at least one 1-cell and at least one 0-cell to define at least one logical expression by the relative positions of the array cells. Length optimized interconnects are added to the array. Each length optimized interconnect terminates at a last leaf cell in the array to which the interconnect makes contact. The leaf cell may be a floating leaf cell in which any pair of abutting cells are electrically isolated from one another until the length optimized interconnects are added to the design. The leaf cell array likely includes a set of rows and a set of columns in which the leaf cells in each row and the set of columns each correspond to an input of the logical expression.
摘要翻译：设计逻辑电路的方法包括提供具有至少一个晶体管的叶单元。叶片适用于逻辑电路中的1单元或0单元。使用至少一个1-单元和至少一个O单元来平铺第一对接叶单元阵列以通过阵列单元的相对位置限定至少一个逻辑表达式。长度优化的互连将添加到阵列中。每个长度优化的互连终止于互连接触到的阵列中的最后一个叶单元格。叶细胞可以是浮叶细胞，其中任何一对邻接细胞彼此电隔离，直到长度优化的互连被添加到设计中。叶单元阵列可能包括一组行和一组列，其中每行中的叶单元和列组各自对应于逻辑表达式的输入。

3. 发明授权

US06825695B1 Unified local clock buffer structures 失效
标题翻译：统一本地时钟缓冲结构
公开(公告)号：US06825695B1
公开(公告)日：2004-11-30
申请号：US10455170
申请日：2003-06-05
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： H03K19096
CPC分类号： G06F1/10
摘要： Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.
摘要翻译：公开了几个本地时钟缓冲器，每个本地时钟缓冲器包括输入部分和输出部分。输入部分基本相同，包括控制逻辑和门控逻辑。控制逻辑产生取决于多个控制信号和时间延迟的全局时钟信号的选通信号。门控逻辑产生取决于全局时钟信号和门控信号的中间时钟信号。输出部分根据中间时钟信号产生至少一个本地时钟信号。在一个实施例中，输出部分产生取决于中间时钟信号的第一本地时钟信号和取决于第一本地时钟信号的第二本地时钟信号。在另一个实施例中，选通逻辑根据全局时钟和门控信号以及反馈信号产生中间时钟信号。输出部分产生反馈信号和一个或多个本地时钟信号。

4. 发明授权

US6104213A Domino logic circuit having a clocked precharge 失效
标题翻译：多米诺逻辑电路具有时钟预充电
公开(公告)号：US6104213A
公开(公告)日：2000-08-15
申请号：US32820
申请日：1998-03-02
申请人： Sang Hoo Dhong , Uttam Shyamalindu Ghoshal , Joel Abraham Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Uttam Shyamalindu Ghoshal , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： H03K19/096 , H03K3/01 , H03K19/0175
CPC分类号： H03K19/0963
摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharger transistor, several input transistors, and an invertor. Connected to a power supply, the precharge transistor receives a first clock input. The discharge transistor, connected to the ground, receives a second clock input. The input transistors is coupled between the precharge transistor and the discharge transistor. Each of the input transistors receives a signal input. The inverter has an input coupled to the precharge transistor, and an output to yield a signal output. The inverter includes a first transistor and a second transistor connected in series, and the output of the inverter is connected to a body of the first transistor.
摘要翻译：公开了具有时钟预充电的多米诺骨牌逻辑电路。多米诺逻辑电路包括预充电晶体管，放电晶体管，多个输入晶体管和反相器。连接到电源，预充电晶体管接收第一时钟输入。连接到地的放电晶体管接收第二个时钟输入。输入晶体管耦合在预充电晶体管和放电晶体管之间。每个输入晶体管接收信号输入。反相器具有耦合到预充电晶体管的输入端和产生信号输出的输出端。逆变器包括串联连接的第一晶体管和第二晶体管，反相器的输出端连接到第一晶体管的主体。

5. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

6. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

7. 发明授权

US07165006B2 Scan chain disable function for power saving 失效
标题翻译：扫描链禁用功能进行省电
公开(公告)号：US07165006B2
公开(公告)日：2007-01-16
申请号：US10976259
申请日：2004-10-28
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： G06F19/00
CPC分类号： G06F1/3203 , G06F1/325
摘要： An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.
摘要翻译：提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。因此，扫描控制信号可以在功能模式下禁用扫描链。

8. 发明授权

US5771268A High speed rotator with array method 失效
标题翻译：高速旋转器阵列法
公开(公告)号：US5771268A
公开(公告)日：1998-06-23
申请号：US762910
申请日：1996-12-10
申请人： Naoaki Aoki , Osamu Takahashi , Joel Abraham Silberman , Sang Hoo Dhong
发明人： Naoaki Aoki , Osamu Takahashi , Joel Abraham Silberman , Sang Hoo Dhong
IPC分类号： G11C19/38 , G11C19/00
CPC分类号： G11C19/38
摘要： A high-speed rotator array for shifting input data a specified amount. The rotator array includes a plurality of straight shift control lines extending across the array for receiving shift data representative of shift values, and a plurality of input terminals for receiving input data to be shifted. The rotator array also includes a plurality of data lines coupled to the plurality of input terminals that extend both diagonally and horizontally across the array. In response to the rotator array receiving the shift data and the input data, a plurality of output terminals transmit the shifted output data.
摘要翻译：用于将输入数据移位一定量的高速旋转器阵列。旋转器阵列包括跨越阵列延伸的多个直移位控制线，用于接收代表移位值的移位数据，以及多个用于接收要移位的输入数据的输入端。旋转器阵列还包括耦合到多个输入端子的多条数据线，跨越阵列沿对角线和水平方向延伸。响应于接收到移位数据和输入数据的旋转体阵列，多个输出端子发送移位的输出数据。

9. 发明授权

US08136061B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US08136061B2
公开(公告)日：2012-03-13
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

10. 发明授权

US06944088B2 Apparatus and method for generating memory access signals, and memory accessed using said signals 失效
标题翻译：用于产生存储器访问信号的装置和方法，以及使用所述信号访问的存储器
公开(公告)号：US06944088B2
公开(公告)日：2005-09-13
申请号：US10262500
申请日：2002-09-30
申请人： Toru Asano , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi
IPC分类号： G06F9/355 , G06F12/08 , G11C8/10 , G11C8/00
CPC分类号： G06F9/355 , G06F12/0895 , G11C8/10
摘要： A sum decoder is disclosed including multiple sum predecoders, a carry generator, and multiple rotate logic units. Each sum predecoder receives multiple bit pairs of non-overlapping segments of a first and second address signal, and produces an input signal dependent upon the bit pairs. The carry generator receives a lower-ordered portion of the first and second address signals, and generates multiple carry signals each corresponding to a different one of the sum predecoders. Each rotate logic unit receives the input signal produced by a corresponding sum predecoders and a corresponding one of the carry signals, rotates the bits of the input signal dependent upon the carry signal, and produces either the input signal or the rotated input signal as an output signal. A memory is described including the sum decoder, a final decode block, and a data array. The final decode block performs logical operations on the output signals of the sum decoder to produce selection signals. Each of the selection signals activates a word line of the data array. A method is disclosed for producing signals for accessing a memory. Highest ordered portions of the first and second address signals are divided into multiple non-overlapping segments. An input signal (i.e., an I term) is generated for each of the segments, as is a carry signal. For each of the segments, when the corresponding carry signal is set, the corresponding I term is rotated one bit position. The I terms are produced as the signals.
摘要翻译：公开了一种和解解码器，其包括多个和预测解码器，进位发生器和多个旋转逻辑单元。每个和预解码器接收第一和第二地址信号的非重叠段的多个比特对，并且根据比特对产生输入信号。进位发生器接收第一和第二地址信号的低阶部分，并且产生每个对应于预测解码器中的不同一个的多个进位信号。每个旋转逻辑单元接收由相应的和预测码器和相应的一个进位信号产生的输入信号，根据进位信号旋转输入信号的位，并产生输入信号或旋转的输入信号作为输出信号。描述包括和解码器，最终解码块和数据阵列的存储器。最终解码块对和解码器的输出信号执行逻辑运算以产生选择信号。每个选择信号激活数据阵列的字线。公开了一种用于产生访问存储器的信号的方法。第一和第二地址信号的最高有序部分被分成多个非重叠段。对于每个段产生输入信号（即I项），进位信号也是如此。对于每个段，当相应的进位信号被设置时，对应的I项被旋转一位位置。我的条款是作为信号产生的。

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