专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06877143B1 System and method for timing abstraction of digital logic circuits 有权
标题翻译：数字逻辑电路定时抽象的系统和方法
公开(公告)号：US06877143B1
公开(公告)日：2005-04-05
申请号：US10226632
申请日：2002-08-23
申请人： Robert J Palermo , Karem A. Sakallah , Shekaripuram V. Venkatesh , Mohammad Mortazavi
发明人： Robert J Palermo , Karem A. Sakallah , Shekaripuram V. Venkatesh , Mohammad Mortazavi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.
摘要翻译：计算机实现的方法提取数字逻辑电路内部的锁存器的时序约束，从而产生时钟表征模型。接收包含在数字逻辑电路中的锁存器和组合逻辑电路的定时信息（例如传播延迟，设置和保持要求），以及用于为电路计时的一类时钟方案的描述。为时钟方案类选择时钟参数。数字逻辑电路的内部时序约束表示为时钟参数的函数的时序约束表达式。这些表达式被组合以定义以时钟参数表示的可行时钟操作的区域。

2. 发明授权

US06442739B1 System and method for timing abstraction of digital logic circuits 有权
标题翻译：数字逻辑电路定时抽象的系统和方法
公开(公告)号：US06442739B1
公开(公告)日：2002-08-27
申请号：US09215633
申请日：1998-12-17
申请人： Robert J. Palermo , Karem A. Sakallah , Shekaripuram V. Venkatesh , Mohammad Mortazavi
发明人： Robert J. Palermo , Karem A. Sakallah , Shekaripuram V. Venkatesh , Mohammad Mortazavi
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： A computer-implemented method abstracts the timing constraints for latches internal to a digital logic circuit, resulting in a clock characterization model. Timing information (such as propagation delays, set-up and hold requirements) for latches and combinational logic circuits contained in a digital logic circuit are received, as is a description of a class of clock scheme for clocking the circuit. Clock parameters are selected for the clock scheme class. The internal timing constraints for the digital logic circuit are expressed as timing constraint expressions which are a function of the clock parameters. The expressions are combined to define a region of feasible clock operation expressed in terms of the clock parameters.
摘要翻译：计算机实现的方法提取数字逻辑电路内部的锁存器的时序约束，从而产生时钟表征模型。接收包含在数字逻辑电路中的锁存器和组合逻辑电路的定时信息（例如传播延迟，设置和保持要求），以及用于为电路计时的一类时钟方案的描述。为时钟方案类选择时钟参数。数字逻辑电路的内部时序约束表示为时钟参数的函数的时序约束表达式。这些表达式被组合以定义以时钟参数表示的可行时钟操作的区域。

3. 发明授权

US07346872B2 Functional timing analysis for characterization of virtual component blocks 有权
标题翻译：用于表征虚拟组件块的功能时序分析
公开(公告)号：US07346872B2
公开(公告)日：2008-03-18
申请号：US10255119
申请日：2002-09-24
申请人： Hakan Yalcin , Robert J. Palmero , Karem A. Sakallah , Mohammad S. Mortazavi , Cyrus Bamji
发明人： Hakan Yalcin , Robert J. Palmero , Karem A. Sakallah , Mohammad S. Mortazavi , Cyrus Bamji
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are “close” (i.e., within a specified tolerance) may be combined into a single table or matrix.
摘要翻译：提供了一种用于对虚拟组件块或其他电路模型执行定时分析的系统和方法，其中使用从电路的控制输入获得的功能信息及其有用的组合来提高精度。识别电路块的控制输入和数据输入。每个功能有意义或有用的控制输入组合被应用于电路块，并且数据输入的拓扑延迟仅沿着未被控制输入阻塞的路径确定。沿阻塞路径的延迟被忽略。通过确定源自控制输入的所有路径的拓扑延迟，而不考虑路径阻塞，进一步增加了分析，以减少可能低估数据输入延迟的可能性。最终定时模型可以包括沿着控制输入的每个组合沿着数据路径的最大延迟的组合，以及沿着源自每个控制输入的路径的最大延迟。延迟分析可以考虑不同的输入压摆和负载电容，结果可以以表格或矩阵形式表示。还提供了一种用于缩短时间延迟信息（无论是标量还是表格形式）的有用技术，以简化虚拟组件块或电路模型的时序表征。 “关闭”（即，在指定的公差内）的延迟表或矩阵可以被组合成单个表或矩阵。

4. 发明授权

US08601414B2 Automated scalable verification for hardware designs at the register transfer level 有权
公开(公告)号：US08601414B2
公开(公告)日：2013-12-03
申请号：US12945020
申请日：2010-11-12
申请人： Zaher Andraus , Karem A. Sakallah , Mark Liffiton
发明人： Zaher Andraus , Karem A. Sakallah , Mark Liffiton
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions; and property checking the abstraction model in relation to one or more design properties. When a violation in the electronic circuit is detected by the property checking step, the feasibility of the violation is then checked and, if the violation is deemed infeasible, the abstraction model is refined.

5. 发明授权

US09389983B2 Verification of complex systems that can be described by a finite state transition system 有权
标题翻译：验证可以通过有限状态转换系统描述的复杂系统
公开(公告)号：US09389983B2
公开(公告)日：2016-07-12
申请号：US14093112
申请日：2013-11-29
申请人： Karem A. Sakallah , Suho Lee
发明人： Karem A. Sakallah , Suho Lee
IPC分类号： G06F17/50 , G06F11/36
CPC分类号： G06F11/3604 , G06F11/28 , G06F17/504 , G06F17/505
摘要： A method including the steps of: generating a system model, the model comprising an initial state, a transition between consecutive states and a property function defining a property that should be met for an allowable state, the initial state, transition function and property function each comprising at least one of data, operations and predicates; generating an abstracted model by approximating at least some of the data, operations and predicates with uninterpreted terms, functions and predicates respectively, to generate at least one abstracted initial state, abstracted transition function and abstracted property function within the abstracted model; performing a complete reachability analysis on the abstracted model to determine whether the system can reach an unallowable abstracted state by following the abstracted transition function; and if not, the system is verified as correct; and if so, unabstracting a trace of the transitions from the abstracted initial state to the unallowable abstracted state.
摘要翻译：一种方法，包括以下步骤：生成系统模型，所述模型包括初始状态，连续状态之间的转换和定义适用于允许状态的属性的属性函数，初始状态，转换函数和属性函数包括数据，操作和谓词中的至少一个; 通过分别用未解释的术语，函数和谓词近似至少一些数据，操作和谓词来生成抽象模型，以在抽象模型内生成至少一个抽象的初始状态，抽象过渡函数和抽象属性函数; 对抽象模型进行完整的可达性分析，以确定系统是否可以通过抽象的过渡函数达到不允许的抽象状态; 如果没有，系统验证正确; 如果是这样，从抽象的初始状态到不允许的抽象状态，重新绘制一些过渡的痕迹。

6. 发明申请

US20130145328A1 AUTOMATED SCALABLE VERIFICATION FOR HARDWARE DESIGNS AT THE REGISTER TRANSFER LEVEL 有权
标题翻译：在注册级别的硬件设计的自动可量测验证
公开(公告)号：US20130145328A1
公开(公告)日：2013-06-06
申请号：US12945020
申请日：2010-11-12
申请人： Zaher Andraus , Karem A. Sakallah , Mark Liffiton
发明人： Zaher Andraus , Karem A. Sakallah , Mark Liffiton
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/504
摘要： A system and methods are provided for verifying a hardware design for an electronic circuit. The method may include: providing a hardware design description for the electronic circuit; extracting a set of design constraints from the hardware design description, where the set of design constraints represents the electronic circuit in terms of signals and logical operations performed on the signals; creating an abstraction model from the set of design constraints, where the abstraction model abstracts one or more of the logical operations in the set of design constraints by replacing the abstracted logical operations with uninterpreted functions; and property checking the abstraction model in relation to one or more design properties. When a violation in the electronic circuit is detected by the property checking step, the feasibility of the violation is then checked and, if the violation is deemed infeasible, the abstraction model is refined.
摘要翻译：提供了用于验证电子电路的硬件设计的系统和方法。该方法可以包括：为电子电路提供硬件设计描述; 从硬件设计描述中提取一组设计约束，其中设计约束集合表示对信号执行的信号和逻辑操作的电子电路; 从设计约束集中创建抽象模型，其中抽象模型通过用未解释的函数替换抽象的逻辑运算来抽象设计约束集合中的一个或多个逻辑运算; 以及与一个或多个设计属性相关的抽象模型的属性检查。当通过属性检查步骤检测到电子电路中的违规时，则检查违规的可行性，如果违规被认为不可行，则抽象模型被改进。

7. 发明授权

US06457159B1 Functional timing analysis for characterization of virtual component blocks 有权
标题翻译：用于表征虚拟组件块的功能时序分析
公开(公告)号：US06457159B1
公开(公告)日：2002-09-24
申请号：US09477710
申请日：1999-12-28
申请人： Hakan Yalcin , Robert J. Palmero , Karem A. Sakallah , Mohammad S. Mortazavi , Cyrus Bamji
发明人： Hakan Yalcin , Robert J. Palmero , Karem A. Sakallah , Mohammad S. Mortazavi , Cyrus Bamji
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are “close” (i.e., within a specified tolerance) may be combined into a single table or matrix.
摘要翻译：提供了一种用于对虚拟组件块或其他电路模型执行定时分析的系统和方法，其中使用从电路的控制输入获得的功能信息及其有用的组合来提高精度。识别电路块的控制输入和数据输入。每个功能有意义或有用的控制输入组合被应用于电路块，并且数据输入的拓扑延迟仅沿着未被控制输入阻塞的路径确定。沿阻塞路径的延迟被忽略。通过确定源自控制输入的所有路径的拓扑延迟，而不考虑路径阻塞，进一步增加了分析，以减少可能低估数据输入延迟的可能性。最终定时模型可以包括沿着控制输入的每个组合沿着数据路径的最大延迟的组合，以及沿着源自每个控制输入的路径的最大延迟。延迟分析可以考虑不同的输入压摆和负载电容，结果可以以表格或矩阵形式表示。还提供了一种用于缩短时间延迟信息（无论是标量还是表格形式）的有用技术，以简化虚拟组件块或电路模型的时序表征。 “关闭”（即，在指定的公差内）的延迟表或矩阵可以组合成单个表或矩阵。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式