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1. 发明申请

US20060181421A1 Ultrasonic transmitter and receiver systems and products using the same 有权
公开(公告)号：US20060181421A1
公开(公告)日：2006-08-17
申请号：US11365835
申请日：2006-03-02
申请人： Robert Forcier , Paul Brantner
发明人： Robert Forcier , Paul Brantner
IPC分类号： G08B13/14 , H04R17/00 , G08B13/18
CPC分类号： G08B13/1427 , A01K15/023 , G08B13/2402
摘要： A transceiver preferably embedded within a wearable security watch, PDA, or other device which achieves a variety of wireless ultrasonic and/or radio-frequency based functions, including digital identification and proximity and sensation monitoring of assets, individuals, pets, and the like. The portable or wearable device realizes these functions by periodically polling and receiving information tags within the transmitting distance of the device. The invention can help reduce the likelihood of the theft, loss, or misplacement by detecting that a tag associated with or attached to an entity has left an individual's proximity and sounding an alarm. The device can also assist individuals with sensory impairments, including persons who are deaf, diabetic, and the like, by detecting a tagged entity as it enters the space around an individual, or by detecting environmental stimuli, such as excessive heat in an individual's proximity or vital sign changes, and sounding an alarm.

2. 发明授权

US07498946B2 Ultrasonic transmitter and receiver systems and products using the same 有权
标题翻译：超声波发射机和接收机系统及产品使用相同
公开(公告)号：US07498946B2
公开(公告)日：2009-03-03
申请号：US11365835
申请日：2006-03-02
申请人： Robert Forcier , Paul Brantner
发明人： Robert Forcier , Paul Brantner
IPC分类号： G08B13/14
CPC分类号： G08B13/1427 , A01K15/023 , G08B13/2402
摘要： A transceiver preferably embedded within a wearable security watch, PDA, or other device which achieves a variety of wireless ultrasonic and/or radio-frequency based functions, including digital identification and proximity and sensation monitoring of assets, individuals, pets, and the like. The portable or wearable device realizes these functions by periodically polling and receiving information tags within the transmitting distance of the device. The invention can help reduce the likelihood of the theft, loss, or misplacement by detecting that a tag associated with or attached to an entity has left an individual's proximity and sounding an alarm. The device can also assist individuals with sensory impairments, including persons who are deaf, diabetic, and the like, by detecting a tagged entity as it enters the space around an individual, or by detecting environmental stimuli, such as excessive heat in an individual's proximity or vital sign changes, and sounding an alarm.
摘要翻译：优选地嵌入在可佩戴的安全手表，PDA或其他设备内的收发器，其实现了各种无线超声波和/或基于射频的功能，包括资产，个人，宠物等的数字识别和邻近感觉监测。便携式或可穿戴设备通过在设备的传输距离内周期性地轮询和接收信息标签来实现这些功能。本发明可以通过检测与实体相关联或连接到实体的标签已经离开个人的邻近并发出警报来帮助减少盗窃，丢失或错位的可能性。该装置还可以通过在标记的实体进入个体周围的空间中检测标签的实体，或者通过检测环境刺激，例如个体接近度中的过热来帮助患有感觉障碍的个体，包括聋人，糖尿病患者等或生命体征改变，并发出警报。

3. 发明授权

US07061381B2 Ultrasonic transmitter and receiver systems and products using the same 失效
公开(公告)号：US07061381B2
公开(公告)日：2006-06-13
申请号：US10237175
申请日：2002-09-09
申请人： Robert Forcier , Paul Brantner
发明人： Robert Forcier , Paul Brantner
IPC分类号： G08B13/14
CPC分类号： G08B13/1427 , A01K15/023 , G08B13/2402
摘要： A transceiver preferably embedded within a wearable security watch, PDA, or other device which achieves a variety of wireless ultrasonic and/or radio-frequency based functions, including digital identification and proximity and sensation monitoring of assets, individuals, pets, and the like. The portable or wearable device realizes these functions by periodically polling and receiving information tags within the transmitting distance of the device. The invention can help reduce the likelihood of the theft, loss, or misplacement by detecting that a tag associated with or attached to an entity has left an individual's proximity and sounding an alarm. The device can also assist individuals with sensory impairments, including persons who are deaf, diabetic, and the like, by detecting a tagged entity as it enters the space around an individual, or by detecting environmental stimuli, such as excessive heat in an individual's proximity or vital sign changes, and sounding an alarm.

4. 发明授权

US09018750B2 Thin film structure for high density inductors and redistribution in wafer level packaging 有权
标题翻译：用于高密度电感器的薄膜结构和晶片级封装中的再分配
公开(公告)号：US09018750B2
公开(公告)日：2015-04-28
申请号：US13572376
申请日：2012-08-10
申请人： Robert Forcier , Douglas Scott
发明人： Robert Forcier , Douglas Scott
IPC分类号： H01L27/00 , H01L23/538 , H01L23/522 , H01L23/532 , H01L23/00 , H01L23/525
CPC分类号： H01L23/5389 , H01L23/5227 , H01L23/525 , H01L23/53223 , H01L24/19 , H01L2223/6677 , H01L2224/12105 , H01L2924/1461 , H01L2924/00
摘要： Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
摘要翻译：公开了一种包括晶片衬底和金属堆叠种子层的封装。金属堆叠种子层包括钛薄膜外层。提供与金属堆叠种子层的钛薄膜外层，抗蚀剂层形成电路接触的抗蚀剂层。进一步公开了一种制造封装的方法。形成具有钛薄膜外层的金属堆叠种子层。形成抗蚀剂层以与金属堆叠种子层的钛薄膜外层接触，并且由抗蚀剂层形成电路。

5. 发明申请

US20050269687A1 BUILD-UP STRUCTURES WITH MULTI-ANGLE VIAS FOR CHIP TO CHIP INTERCONNECTS AND OPTICAL BUSSING 失效
公开(公告)号：US20050269687A1
公开(公告)日：2005-12-08
申请号：US11145948
申请日：2005-06-07
申请人： Robert Forcier
发明人： Robert Forcier
IPC分类号： B81B7/00 , B81B7/02 , G02B6/43 , H01L21/60 , H01L23/31 , H01L23/433 , H01L23/538 , H05K1/02 , H05K1/11 , H05K1/18 , H01L23/12
CPC分类号： H05K1/185 , B81C1/0023 , G02B6/43 , H01L23/3128 , H01L23/4334 , H01L23/5389 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/82 , H01L24/83 , H01L2223/6677 , H01L2224/02333 , H01L2224/12105 , H01L2224/16225 , H01L2224/24227 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73267 , H01L2224/83101 , H01L2224/83191 , H01L2224/838 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/10329 , H01L2924/12042 , H01L2924/12043 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/351 , H05K1/0274 , H05K1/115 , H05K1/186 , H05K2201/09836 , H05K2203/061 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/01014 , H01L2924/01031 , H01L2924/3512
摘要： A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.

6. 发明授权

US06919508B2 Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing 失效
标题翻译：具有多角度通孔的堆叠结构，用于芯片到芯片互连和光学总线
公开(公告)号：US06919508B2
公开(公告)日：2005-07-19
申请号：US10704131
申请日：2003-11-10
申请人： Robert Forcier
发明人： Robert Forcier
IPC分类号： B81B7/00 , B81B7/02 , G02B6/43 , H01L21/60 , H01L23/31 , H01L23/433 , H01L23/538 , H05K1/02 , H05K1/11 , H05K1/18 , H01L23/02
CPC分类号： H05K1/185 , B81C1/0023 , G02B6/43 , H01L23/3128 , H01L23/4334 , H01L23/5389 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/82 , H01L24/83 , H01L2223/6677 , H01L2224/02333 , H01L2224/12105 , H01L2224/16225 , H01L2224/24227 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73267 , H01L2224/83101 , H01L2224/83191 , H01L2224/838 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/10329 , H01L2924/12042 , H01L2924/12043 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/351 , H05K1/0274 , H05K1/115 , H05K1/186 , H05K2201/09836 , H05K2203/061 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/01014 , H01L2924/01031 , H01L2924/3512
摘要： A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.
摘要翻译：用于芯片到芯片互连的集成结构和利用多角度通孔的系统级封装，用于电和光路由或电子信息的总线以及包括中间复合材料的受控CTE电介质，以实现单片结构的最佳电气和光学性能。芯片，多芯片，微机电（MEM）和/或其他有源或无源元件如换能器或电容器可以准确地定位在诸如铜散热片的基板上，并且可以将多角螺柱凸块放置在组件。第一电介质层优选地放置在部件上，从而将部件嵌入结构中。通过光刻，激光加工，软光刻或各向异性导电膜接合的各种工艺，在第一金属层上形成逃逸路线和电路。使用多角度通孔形成附加介电层和金属电路，以形成从芯片上的紧密间距接合焊盘到其它有源和无源部件的逃逸路由。多角度通孔可以以数字或模拟电磁电流的形式携带电或光信息，或以可见或不可见的光学总线和互连的形式。

7. 发明授权

US07371970B2 Rigid-flex circuit board system 失效
标题翻译：刚性电路板系统
公开(公告)号：US07371970B2
公开(公告)日：2008-05-13
申请号：US10731390
申请日：2003-12-08
申请人： Jeffrey D. Flammer , Robert Forcier
发明人： Jeffrey D. Flammer , Robert Forcier
IPC分类号： H05K1/03
CPC分类号： H05K3/4691 , H05K1/0278 , H05K1/118 , H05K1/16 , H05K3/0032 , H05K3/0044 , H05K3/0061 , H05K3/429 , H05K2201/09036 , H05K2201/09081 , H05K2201/0909 , H05K2201/09109 , H05K2201/09536 , H05K2201/09745 , H05K2203/1572 , H05K2203/302 , Y10T29/49126
摘要： A rigid-flex circuit board system that can be manufactured using less expensive and more reliable rigid circuit board methods and equipment, and can maintain rigidity and dimensional stability until the time when it is first desired to flex.
摘要翻译：可以使用更便宜和更可靠的刚性电路板方法和设备制造的刚性 - 柔性电路板系统，并且可以保持刚性和尺寸稳定性，直到首次需要弯曲时为止。

8. 发明申请

US20130037956A1 THIN FILM STRUCTURE FOR HIGH DENSITY INDUCTORS AND REDISTRIBUTION IN WAFER LEVEL PACKAGING 有权
标题翻译：用于高密度电感器的薄膜结构和在水平包装中的重新分配
公开(公告)号：US20130037956A1
公开(公告)日：2013-02-14
申请号：US13572376
申请日：2012-08-10
申请人： Robert Forcier , Douglas Scott
发明人： Robert Forcier , Douglas Scott
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/5389 , H01L23/5227 , H01L23/525 , H01L23/53223 , H01L24/19 , H01L2223/6677 , H01L2224/12105 , H01L2924/1461 , H01L2924/00
摘要： Disclosed is a package that includes a wafer substrate and a metal stack seed layer. The metal stack seed layer includes a titanium thin film outer layer. A resist layer is provided in contact with the titanium thin film outer layer of the metal stack seed layer, the resist layer forming circuitry. A method for manufacturing a package is further disclosed. A metal stack seed layer having a titanium thin film outer layer is formed. A resist layer is formed so as to be in contact with the titanium thin film outer layer of the metal stack seed layer, and circuitry is formed from the resist layer.
摘要翻译：公开了一种包括晶片衬底和金属堆叠种子层的封装。金属堆叠种子层包括钛薄膜外层。提供与金属堆叠种子层的钛薄膜外层，抗蚀剂层形成电路接触的抗蚀剂层。进一步公开了一种制造封装的方法。形成具有钛薄膜外层的金属堆叠种子层。形成抗蚀剂层以与金属堆叠种子层的钛薄膜外层接触，并且由抗蚀剂层形成电路。

9. 发明授权

US07011988B2 Build-up structures with multi-angle vias for Chip to Chip interconnects and optical bussing 失效
标题翻译：用于芯片到芯片互连和光学总线的多角度通孔的构建结构
公开(公告)号：US07011988B2
公开(公告)日：2006-03-14
申请号：US11145948
申请日：2005-06-07
申请人： Robert Forcier
发明人： Robert Forcier
IPC分类号： H01L21/44
CPC分类号： H05K1/185 , B81C1/0023 , G02B6/43 , H01L23/3128 , H01L23/4334 , H01L23/5389 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/82 , H01L24/83 , H01L2223/6677 , H01L2224/02333 , H01L2224/12105 , H01L2224/16225 , H01L2224/24227 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73267 , H01L2224/83101 , H01L2224/83191 , H01L2224/838 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/10329 , H01L2924/12042 , H01L2924/12043 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/351 , H05K1/0274 , H05K1/115 , H05K1/186 , H05K2201/09836 , H05K2203/061 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/01014 , H01L2924/01031 , H01L2924/3512
摘要： A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.
摘要翻译：用于芯片到芯片互连的集成结构和利用多角度通孔的系统级封装，用于电和光路由或电子信息的总线以及包括中间复合材料的受控CTE电介质，以实现单片结构的最佳电气和光学性能。芯片，多芯片，微机电（MEM）和/或其他有源或无源元件如换能器或电容器可以准确地定位在诸如铜散热片的基板上，并且可以将多角螺柱凸块放置在组件。第一电介质层优选地放置在部件上，从而将部件嵌入结构中。通过光刻，激光加工，软光刻或各向异性导电膜接合的各种工艺，在第一金属层上形成逃逸路线和电路。使用多角度通孔形成附加介电层和金属电路，以形成从芯片上的紧密间距接合焊盘到其它有源和无源部件的逃逸路由。多角度通孔可以以数字或模拟电磁电流的形式携带电或光信息，或以可见或不可见的光学总线和互连的形式。

10. 发明申请

US20050087356A1 BUILD-UP STRUCTURES WITH MULTI-ANGLE VIAS FOR CHIP TO CHIP INTERCONNECTS AND OPTICAL BUSSING 失效
标题翻译：用于芯片互连和光学总线的多角度VIAS的建立结构
公开(公告)号：US20050087356A1
公开(公告)日：2005-04-28
申请号：US10704131
申请日：2003-11-10
申请人： Robert Forcier
发明人： Robert Forcier
IPC分类号： B81B7/00 , B81B7/02 , G02B6/43 , H01L21/60 , H01L23/31 , H01L23/433 , H01L23/538 , H05K1/02 , H05K1/11 , H05K1/18 , H01L23/02
CPC分类号： H05K1/185 , B81C1/0023 , G02B6/43 , H01L23/3128 , H01L23/4334 , H01L23/5389 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/82 , H01L24/83 , H01L2223/6677 , H01L2224/02333 , H01L2224/12105 , H01L2224/16225 , H01L2224/24227 , H01L2224/2919 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73267 , H01L2224/83101 , H01L2224/83191 , H01L2224/838 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/10329 , H01L2924/12042 , H01L2924/12043 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/351 , H05K1/0274 , H05K1/115 , H05K1/186 , H05K2201/09836 , H05K2203/061 , H01L2224/83 , H01L2224/82 , H01L2924/00 , H01L2924/01014 , H01L2924/01031 , H01L2924/3512
摘要： A build-up structure for chip to chip interconnects and System-In-Package utilizing multi-angle vias for electrical and optical routing or bussing of electronic information and controlled CTE dielectrics including mesocomposites to achieve optimum electrical and optical performance of monolithic structures. Die, multiple die, Microelectromechanical Machines (MEMs) and/or other active or passive components such as transducers or capacitors can be accurately positioned on a substrate such as a copper heatsink and multi-angle stud bumps can be placed on the active sites of the components. A first dielectric layer is preferably placed on the components, thereby embedding the components in the structure. Through various processes of photolithography, laser machining, soft lithography or anisotropic conductive film bonding, escape routing and circuitry is formed on the first metal layer. Additional dielectric layers and metal circuitry are formed utilizing multi-angle vias to form escape routing from tight pitch bond pads on the die to other active and passive components. Multi-angle vias can carry electrical or optical information in the form of digital or analog electromagnetic current, or in the form of visible or non-visible optical bussing and interconnections.
摘要翻译：用于芯片到芯片互连的集成结构和利用多角度通孔的系统级封装，用于电和光路由或电子信息的总线以及包括中间复合材料的受控CTE电介质，以实现单片结构的最佳电气和光学性能。芯片，多芯片，微机电（MEM）和/或其他有源或无源元件如换能器或电容器可以准确地定位在诸如铜散热片的基板上，并且可以将多角螺柱凸块放置在组件。第一电介质层优选地放置在部件上，从而将部件嵌入结构中。通过光刻，激光加工，软光刻或各向异性导电膜接合的各种工艺，在第一金属层上形成逃逸路线和电路。使用多角度通孔形成附加介电层和金属电路，以形成从芯片上的紧密间距接合焊盘到其它有源和无源部件的逃逸路由。多角度通孔可以以数字或模拟电磁电流的形式携带电或光信息，或以可见或不可见的光学总线和互连的形式。

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