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1. 发明授权

US08347124B2 Workload power consumption projection on information handling system 有权
标题翻译：信息处理系统的工作负载功耗预测
公开(公告)号：US08347124B2
公开(公告)日：2013-01-01
申请号：US12650928
申请日：2009-12-31
申请人： Robert Bell, Jr. , Donald DeSota , Rajendra Panda , Joseph Robichaux , Venkat Indukuru , Sameh Sharkawi
发明人： Robert Bell, Jr. , Donald DeSota , Rajendra Panda , Joseph Robichaux , Venkat Indukuru , Sameh Sharkawi
IPC分类号： G06F1/00
CPC分类号： G06F1/28
摘要： The projected power consumption for an application program running on a future IHS is determined by generating a power proxy for the application program, and power proxies for a plurality of standard benchmarks. An algorithm correlates the power proxy for the application program, and the power proxies for the standard benchmarks to generate weighted surrogates that are combined with power proxies derived from running the benchmark surrogates on the future IHS to generate the projected power consumption.
摘要翻译：通过生成应用程序的电源代理以及多个标准基准的电源代理来确定在未来IHS上运行的应用程序的预计功耗。算法将应用程序的功率代理和标准基准的功率代理相关联，以生成与未来IHS运行基准代理产生的功率代理相结合的加权代理，以生成预计的功耗。

2. 发明申请

US20110154067A1 WORKLOAD POWER CONSUMPTION PROJECTION ON INFORMATION HANDLING SYSTEM 有权
标题翻译：信息处理系统的工作量消耗预测
公开(公告)号：US20110154067A1
公开(公告)日：2011-06-23
申请号：US12650928
申请日：2009-12-31
申请人： Robert Bell, JR. , Donald DeSota , Rajendra Panda , Joseph Robichaux , Venkat Indukuru , Sameh Sharkawi
发明人： Robert Bell, JR. , Donald DeSota , Rajendra Panda , Joseph Robichaux , Venkat Indukuru , Sameh Sharkawi
IPC分类号： G06F1/00
CPC分类号： G06F1/28
摘要： The projected power consumption for an application program running on a future IHS is determined by generating a power proxy for the application program, and power proxies for a plurality of standard benchmarks. An algorithm correlates the power proxy for the application program, and the power proxies for the standard benchmarks to generate weighted surrogates that are combined with power proxies derived from running the benchmark surrogates on the future IHS to generate the projected power consumption.
摘要翻译：通过生成应用程序的电源代理以及多个标准基准的电源代理来确定在未来IHS上运行的应用程序的预计功耗。算法将应用程序的功率代理和标准基准的功率代理相关联，以生成与未来IHS运行基准代理产生的功率代理相结合的加权代理，以生成预计的功耗。

3. 发明申请

US20060101209A1 Prefetch miss indicator for cache coherence directory misses on external caches 失效
标题翻译：高速缓存一致性目录丢失的外部缓存的预取缺失指示符
公开(公告)号：US20060101209A1
公开(公告)日：2006-05-11
申请号：US10983350
申请日：2004-11-08
申请人： Eric Lais , Donald DeSota , Rob Joersz
发明人： Eric Lais , Donald DeSota , Rob Joersz
IPC分类号： G06F13/28
CPC分类号： G06F12/082 , G06F2212/507
摘要： A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluated results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.
摘要翻译：用于减少与共享分布式存储器数据处理系统中的外部高速缓存上的高速缓存一致性目录丢失相关的延迟的系统，方法和制品。评估缓存一致性目录可能将目录条目预取到目录缓存中。如果预取的预取导致目录错过，则设置预取缺失指示符。在随后处理与目录条目相对应的存储器块请求时，查阅预取缺失指示符。如果预取缺失指示符被设置，则采取加速侦听响应动作。从而避免了否则将要求的缓存一致性目录中的第二次查找的等待时间。

4. 发明申请

US20060129739A1 Method controller having tables mapping memory addresses to memory modules 失效
标题翻译：方法控制器具有将存储器地址映射到存储器模块的表
公开(公告)号：US20060129739A1
公开(公告)日：2006-06-15
申请号：US11010205
申请日：2004-12-11
申请人： Eric Lais , Donald DeSota , Michael Grassi , Bruce Gilbert
发明人： Eric Lais , Donald DeSota , Michael Grassi , Bruce Gilbert
IPC分类号： G06F12/06
CPC分类号： G06F12/0653 , G06F13/1668
摘要： A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.
摘要翻译：存储器控制器包括端口和对应的表。每个端口都接受一个或多个内存模块。每个表包括将内存地址映射到内存模块的条目。每个条目对应于不超过一个内存模块。这些表支持端口内存模块的非对称数量; 每个端口能够相对于其他端口具有不同数量的存储器模块。这些表对数字和位置方面的内存模块在端口中插入的位置没有任何限制。表可独立配置; 每个表的配置可以独立于其他表的配置进行修改。每个表都是可动态配置的。表的条目是可修改的，以反映连接的内存模块的数量和类型的变化，而不会重新启动或暂时中止包含内存控制器的计算机系统。

5. 发明申请

US20050125695A1 Non-inline transaction error correction 有权
标题翻译：非内联交易纠错
公开(公告)号：US20050125695A1
公开(公告)日：2005-06-09
申请号：US10730815
申请日：2003-12-08
申请人： Bruce Gilbert , Donald DeSota , Robert Joersz
发明人： Bruce Gilbert , Donald DeSota , Robert Joersz
IPC分类号： H04L9/00 , H04L9/32
CPC分类号： G06F11/0724 , G06F11/0712 , G06F11/0793 , G06F11/1407 , G06F11/141
摘要： Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.
摘要翻译：公开了非内联事务纠错。在管道中处理的事务被确定为包括可校正错误的情况下，将其从流水线输出或排出到错误队列中。流水线从正常操作模式切换到校正操作模式。在校正模式中，校正命令被插入管道内并在流水线内处理以校正事务内的错误。流水线从校正操作模式切换到重启操作模式。在重新启动模式下，事务在流水线内重新处理。然后将管道从重新启动模式切换回正常操作模式。

6. 发明申请

US20050120183A1 Local region table for storage of information regarding memory access by other nodes 失效
标题翻译：用于存储有关其他节点存储器访问的信息的本地区域表
公开(公告)号：US20050120183A1
公开(公告)日：2005-06-02
申请号：US10725853
申请日：2003-12-01
申请人： Donald DeSota , William Durr , Robert Joersz , Davis Miller
发明人： Donald DeSota , William Durr , Robert Joersz , Davis Miller
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0817 , G06F12/082
摘要： The local storage of information regarding memory access by other nodes within a coherency controller of a node is disclosed. The coherency controller receives a transaction relating a line of local memory of the node. In response to locally determining that the line of the local memory is not being cached by another node and/or has not been modified by another node, the coherency controller processes the transaction without accessing tag directory information regarding the line. A table within the controller may store entries corresponding to local memory sections. Each entry includes a count value tracking a number of lines of the section being cached by other nodes, and a count value tracking a number of lines of the section that have been modified by other nodes. The table may also include flags corresponding to the sections, each flag indicating the validity of the section's contents.
摘要翻译：公开了关于节点的一致性控制器内的其他节点的存储器访问的信息的本地存储。一致性控制器接收与该节点的一行本地存储器相关的事务。响应于本地确定本地存储器的行不被另一个节点缓存和/或尚未被另一个节点修改，一致性控制器处理该事务而不访问关于该行的标签目录信息。控制器内的表可以存储对应于本地存储器部分的条目。每个条目包括跟踪由其他节点缓存的段的数量的计数值，以及跟踪由其他节点修改的段的数量的计数值。该表还可以包括对应于这些部分的标志，每个标志指示该部分的内容的有效性。

7. 发明申请

US20070286327A1 Implementation-efficient multiple-counter value hardware performance counter 失效
标题翻译：实现高效的多计数器硬件性能计数器
公开(公告)号：US20070286327A1
公开(公告)日：2007-12-13
申请号：US11738497
申请日：2007-04-22
申请人： Carl Love , Donald DeSota , Jaeheon Jeong , Russell Clapp
发明人： Carl Love , Donald DeSota , Jaeheon Jeong , Russell Clapp
IPC分类号： H03K21/38
CPC分类号： G06F11/3466 , G06F2201/88
摘要： An implementation-efficient, multiple-counter value hardware performance counter is disclosed. A hardware counter of one embodiment includes a memory array and a hardware incrementer. The array stores counter values that are indexable by an index constructed based at least on the number of events to which the counter values correspond. The index may be constructed as a concatenation of a number of bits binarily representing the number of events, and a number of bits binarily representing the number of qualifiers to the events. The incrementer reads the counter values from the array, increments the counter values, and writes the resulting counter values back into the array. The array may be divided into banks over which the counter values are stored, where each bank has a separate instance of the incrementer. Each bank may have a separate instance of the index that indexes only those counters stored in the bank.
摘要翻译：公开了一种实现高效的多计数器硬件性能计数器。一个实施例的硬件计数器包括存储器阵列和硬件递增器。阵列存储可由至少基于计数器值对应的事件数构成的索引可索引的计数器值。索引可以被构造为二进制数表示事件数量的位数的连接，以及二进制表示事件的限定符的数目的位数。增量器从数组中读取计数器值，增加计数器值，并将生成的计数器值写入数组。阵列可以被划分为存储有计数器值的存储体，其中每个存储体具有加法器的单独实例。每个银行可能有一个单独的索引实例，仅索引存储在银行中的那些计数器。

8. 发明申请

US20050273669A1 Cache entry error-correcting code (ECC) based at least on cache entry data and memory address 有权
公开(公告)号：US20050273669A1
公开(公告)日：2005-12-08
申请号：US11203333
申请日：2005-08-13
申请人： Donald DeSota
发明人： Donald DeSota
IPC分类号： G06F11/10 , G06F12/08 , G06F12/16
CPC分类号： G06F12/0802 , G06F11/1064
摘要： Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A cache entry for a desired memory address is retrieved. The cache entry includes data and a stored ECC based on the data and a memory address. An ECC is determined based at least on the data of the cache entry and the desired memory address. If the ECC at least based on the cache entry data and the desired memory address equals the stored ECC, then the cache entry caches the desired memory address without error.

9. 发明申请

US20050283783A1 Method for optimizing pipeline use in a multiprocessing system 审中-公开
标题翻译：在多处理系统中优化管道使用的方法
公开(公告)号：US20050283783A1
公开(公告)日：2005-12-22
申请号：US10874029
申请日：2004-06-22
申请人： Donald DeSota
发明人： Donald DeSota
IPC分类号： G06F9/46
CPC分类号： G06F9/3851
摘要： A value tracking memory region within system memory is created to manage select locks and threads waiting for access to one or more of the select locks. When a thread requests access to an unavailable select lock, the thread will be stalled in the value tracking memory region. The stall process optimizes pipeline use by eliminating the process of a thread spinning on a lock, which utilizes pipeline resources.
摘要翻译：创建系统存储器内的值跟踪存储器区域，以管理等待访问一个或多个选择锁的选择锁和线程。当线程请求访问不可用的选择锁时，线程将在值跟踪存储器区域停滞。停顿过程通过消除使用管道资源的锁上的线程旋转的过程来优化管道使用。

10. 发明申请

US20050149603A1 Queuing of conflicted remotely received transactions 有权
标题翻译：排队冲突的远程接收交易
公开(公告)号：US20050149603A1
公开(公告)日：2005-07-07
申请号：US10739699
申请日：2003-12-18
申请人： Donald DeSota , Robert Joersz , Davis Miller , Maged Michael
发明人： Donald DeSota , Robert Joersz , Davis Miller , Maged Michael
IPC分类号： G06F15/16
CPC分类号： G06F15/173
摘要： A method of queuing of received transactions that have a resource conflict is disclosed. A first node receives a first transaction from a second node, where the first transaction relates to a resource of the first node. The transaction may be a request relating to a memory line of the first node, for instance. It is determined that a second transaction that relates to this resource of the first node is already being processed by the first node. Therefore, the first transaction is enqueued in a conflict queue within the first node. The queuing may be a linked list, a priority queue, or another type of queue. Once the second transaction has been processed, the first transaction is restarted for processing by the first node. The first transaction is then processed by the first node.
摘要翻译：公开了对资源冲突的接收到的事务进行排队的方法。第一节点从第二节点接收第一事务，其中第一事务涉及第一节点的资源。例如，事务可以是与第一节点的存储器线有关的请求。确定与第一节点的该资源相关的第二事务已被第一节点处理。因此，第一个事务在第一个节点内的冲突队列中排队。排队可以是链接列表，优先级队列或其他类型的队列。一旦处理了第二个事务，第一个事务就被重新启动，由第一个节点处理。第一个事务由第一个节点处理。

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