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1. 发明申请

US20070121660A1 Load balanced architecture of cascading of MxM Ethernet packet based switches that supports up to 4 levels of QoS 审中-公开
标题翻译：负载均衡的MxM以太网数据包交换机级联架构，支持多达4个QoS级别
公开(公告)号：US20070121660A1
公开(公告)日：2007-05-31
申请号：US11593807
申请日：2006-11-06
申请人： Robert Ayrapetian , Serob Douvalian
发明人： Robert Ayrapetian , Serob Douvalian
IPC分类号： H04L12/56
CPC分类号： H04L49/351 , H04L49/1515 , H04L49/205
摘要： A network switch is provided that includes a bank of input switches configured to receive variable length data packets; a bank of central switches configured to receive packets from the input switches in a distributed manner; and a bank of output switches configured to receive and output variable length packets from the bank of central switches.
摘要翻译：提供一种网络交换机，其包括被配置为接收可变长度数据分组的一组输入交换机; 一组中央交换机，被配置为以分布式方式从输入交换机接收分组; 以及一组输出开关，被配置为从中央交换机组接收和输出可变长度分组。

2. 发明申请

US20100034208A1 Buffered Crossbar Switch With a Linear Buffer to Port Relationship that Supports Cells and Packets of Variable Size 审中-公开
标题翻译：缓冲交叉开关带有线性缓冲区到端口关系，支持单元格和可变大小的数据包
公开(公告)号：US20100034208A1
公开(公告)日：2010-02-11
申请号：US12356185
申请日：2009-01-20
申请人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
发明人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
IPC分类号： H04L12/56
CPC分类号： H04L49/3036 , H04L49/101 , H04L49/30 , H04L49/3009 , H04L49/3027 , H04L49/3045 , H04L49/503
摘要： A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.
摘要翻译：缓冲交叉开关具有支持可变大小的单元和数据包的缓冲区到端口关系。提供了一种新颖的调度器，其允许有效的交叉开关，其中内部缓冲器的数量之间的关系小于端口平方的数量。这允许可实现需要较少缓冲存储器的开关。

3. 发明申请

US20060256783A1 Buffered crossbar switch with a linear buffer to port relationship that supports cells and packets of variable size 失效
公开(公告)号：US20060256783A1
公开(公告)日：2006-11-16
申请号：US11400367
申请日：2006-04-06
申请人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
发明人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
IPC分类号： H04L12/50 , H04L12/56
CPC分类号： H04L49/3036 , H04L49/101 , H04L49/30 , H04L49/3009 , H04L49/3027 , H04L49/3045 , H04L49/503
摘要： A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.

4. 发明授权

US07499464B2 Buffered crossbar switch with a linear buffer to port relationship that supports cells and packets of variable size 失效
标题翻译：缓冲交叉开关带有线性缓冲区到端口关系，支持可变大小的单元和数据包
公开(公告)号：US07499464B2
公开(公告)日：2009-03-03
申请号：US11400367
申请日：2006-04-06
申请人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
发明人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
IPC分类号： H04L12/28
CPC分类号： H04L49/3036 , H04L49/101 , H04L49/30 , H04L49/3009 , H04L49/3027 , H04L49/3045 , H04L49/503
摘要： A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.
摘要翻译：缓冲交叉开关具有支持可变大小的单元和数据包的缓冲区到端口关系。提供了一种新颖的调度器，其允许有效的交叉开关，其中内部缓冲器的数量之间的关系小于端口平方的数量。这允许可实现需要较少缓冲存储器的开关。

5. 发明申请

US20070140260A1 System and method of single switch string hardware 审中-公开
标题翻译：单开关串硬件的系统和方法
公开(公告)号：US20070140260A1
公开(公告)日：2007-06-21
申请号：US11593858
申请日：2006-11-06
申请人： Simon Duxbury , Robert Ayrapetian , Serob Douvalian
发明人： Simon Duxbury , Robert Ayrapetian , Serob Douvalian
IPC分类号： H04L12/56
CPC分类号： H04L49/252 , H04L49/251 , H04L49/3027
摘要： An improved string switch architecture is provided having a partial shared memory. The string switch includes a plurality of input ports configured to classify incoming packets, wherein the destination output port and priority is determined at classification; a plurality of output ports, each having a string bank of memory units that compose the aggregate output queue memory for each port; a write manager configured to receive write requests and to write each packet directly to the appropriate memory location within each output port; where each output port includes an assignment block configured to receive packets originating from each input port; and a read manager configured to read data from the plurality of output ports. The write manager may be configured to write packet data received in a round robin fashion, which may be independent from the packet protocol.
摘要翻译：提供了具有部分共享存储器的改进的字符串开关体系结构。字符串开关包括多个输入端口，其被配置为对输入分组进行分类，其中，目的地输出端口和优先级被分类确定; 多个输出端口，每个输出端口具有构成每个端口的汇总输出队列存储器的字符串存储单元组; 写管理器被配置为接收写请求并将每个数据包直接写入每个输出端口内的相应存储器位置; 其中每个输出端口包括被配置为接收源自每个输入端口的分组的分配块; 以及被配置为从所述多个输出端口读取数据的读取管理器。写管理器可以被配置为写入以循环方式接收的分组数据，其可以独立于分组协议。

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