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1. 发明授权

US08077646B1 Equalization in a wireless multiple access communication system 有权
标题翻译：无线多址通信系统中的均衡
公开(公告)号：US08077646B1
公开(公告)日：2011-12-13
申请号：US12167911
申请日：2008-07-03
申请人： Raphael Cendrillon , Robert Ayrapetian
发明人： Raphael Cendrillon , Robert Ayrapetian
IPC分类号： H04B7/00
CPC分类号： H04L25/03159 , H04L5/0007 , H04L5/0037 , H04L25/03012 , H04L27/2607 , H04L27/2627 , H04L27/2649 , H04L27/2662 , H04L2025/03414 , H04L2025/03611
摘要： An equalization method and apparatus for a communication system having a first transceiver device that communicates with each of a plurality of second transceiver devices receives a data transmission over a subset of frequency sub-carriers allotted to each second transceiver device. The communication channel between first transceiver device and the plurality of second transceiver devices is partitioned in a plurality of frequency sub-carriers of which the frequency sub-carriers allotted to a second transceiver device is a subset. The data transmission is transformed from a time-domain transmission to a frequency domain transmission. An equalization filter is applied separately to each of the frequency sub-carriers within the subset of frequency sub-carriers.
摘要翻译：用于具有与多个第二收发器装置中的每一个通信的第一收发器装置的通信系统的均衡方法和装置在分配给每个第二收发器装置的频率子载波的子集上接收数据传输。第一收发器设备和多个第二收发器设备之间的通信信道被划分成多个频率子载波，其中分配给第二收发器设备的频率子载波是子集。数据传输从时域传输变换到频域传输。均衡滤波器分别应用于频率子载波子集内的每个频率子载波。

2. 发明申请

US20100034208A1 Buffered Crossbar Switch With a Linear Buffer to Port Relationship that Supports Cells and Packets of Variable Size 审中-公开
标题翻译：缓冲交叉开关带有线性缓冲区到端口关系，支持单元格和可变大小的数据包
公开(公告)号：US20100034208A1
公开(公告)日：2010-02-11
申请号：US12356185
申请日：2009-01-20
申请人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
发明人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
IPC分类号： H04L12/56
CPC分类号： H04L49/3036 , H04L49/101 , H04L49/30 , H04L49/3009 , H04L49/3027 , H04L49/3045 , H04L49/503
摘要： A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.
摘要翻译：缓冲交叉开关具有支持可变大小的单元和数据包的缓冲区到端口关系。提供了一种新颖的调度器，其允许有效的交叉开关，其中内部缓冲器的数量之间的关系小于端口平方的数量。这允许可实现需要较少缓冲存储器的开关。

3. 发明申请

US20060256783A1 Buffered crossbar switch with a linear buffer to port relationship that supports cells and packets of variable size 失效
公开(公告)号：US20060256783A1
公开(公告)日：2006-11-16
申请号：US11400367
申请日：2006-04-06
申请人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
发明人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
IPC分类号： H04L12/50 , H04L12/56
CPC分类号： H04L49/3036 , H04L49/101 , H04L49/30 , H04L49/3009 , H04L49/3027 , H04L49/3045 , H04L49/503
摘要： A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.

4. 发明授权

US07499464B2 Buffered crossbar switch with a linear buffer to port relationship that supports cells and packets of variable size 失效
标题翻译：缓冲交叉开关带有线性缓冲区到端口关系，支持可变大小的单元和数据包
公开(公告)号：US07499464B2
公开(公告)日：2009-03-03
申请号：US11400367
申请日：2006-04-06
申请人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
发明人： Robert Ayrapetian , Edward Ayrapetian , Serob Douvalian
IPC分类号： H04L12/28
CPC分类号： H04L49/3036 , H04L49/101 , H04L49/30 , H04L49/3009 , H04L49/3027 , H04L49/3045 , H04L49/503
摘要： A buffered crossbar switch is provided with a buffer to port relationship that supports cells and packets of variable size. A novel scheduler is provided that allows for an efficient crossbar switch, where the relationship between the number of internal buffers is less than the number of ports squared. This allows for a switch that can be implemented that requires less buffer memory.
摘要翻译：缓冲交叉开关具有支持可变大小的单元和数据包的缓冲区到端口关系。提供了一种新颖的调度器，其允许有效的交叉开关，其中内部缓冲器的数量之间的关系小于端口平方的数量。这允许可实现需要较少缓冲存储器的开关。

5. 发明申请

US20070140260A1 System and method of single switch string hardware 审中-公开
标题翻译：单开关串硬件的系统和方法
公开(公告)号：US20070140260A1
公开(公告)日：2007-06-21
申请号：US11593858
申请日：2006-11-06
申请人： Simon Duxbury , Robert Ayrapetian , Serob Douvalian
发明人： Simon Duxbury , Robert Ayrapetian , Serob Douvalian
IPC分类号： H04L12/56
CPC分类号： H04L49/252 , H04L49/251 , H04L49/3027
摘要： An improved string switch architecture is provided having a partial shared memory. The string switch includes a plurality of input ports configured to classify incoming packets, wherein the destination output port and priority is determined at classification; a plurality of output ports, each having a string bank of memory units that compose the aggregate output queue memory for each port; a write manager configured to receive write requests and to write each packet directly to the appropriate memory location within each output port; where each output port includes an assignment block configured to receive packets originating from each input port; and a read manager configured to read data from the plurality of output ports. The write manager may be configured to write packet data received in a round robin fashion, which may be independent from the packet protocol.
摘要翻译：提供了具有部分共享存储器的改进的字符串开关体系结构。字符串开关包括多个输入端口，其被配置为对输入分组进行分类，其中，目的地输出端口和优先级被分类确定; 多个输出端口，每个输出端口具有构成每个端口的汇总输出队列存储器的字符串存储单元组; 写管理器被配置为接收写请求并将每个数据包直接写入每个输出端口内的相应存储器位置; 其中每个输出端口包括被配置为接收源自每个输入端口的分组的分配块; 以及被配置为从所述多个输出端口读取数据的读取管理器。写管理器可以被配置为写入以循环方式接收的分组数据，其可以独立于分组协议。

6. 发明授权

US08705676B2 Method and apparatus for clock recovery in XDSL transceivers 失效
标题翻译： XDSL收发器中时钟恢复的方法和装置
公开(公告)号：US08705676B2
公开(公告)日：2014-04-22
申请号：US12802884
申请日：2010-06-15
申请人： Robert Ayrapetian , Qasem Aldrubi , Hossein Dehghan-Fard , Christopher Chow
发明人： Robert Ayrapetian , Qasem Aldrubi , Hossein Dehghan-Fard , Christopher Chow
IPC分类号： H04L7/00
CPC分类号： H04L27/2657 , H04L27/2676
摘要： A multi-tone transceiver including: a transform component, a tone selector, an error detector, an aggregator and an oscillator. The transform component transforms received communications from the time domain to the frequency domain. The tone selector selects a sub-set of the received tones which exhibit an elevated signal-to-noise ratio (SNR) as a clock recovery tone set (CRTS) and drops and add tones to the CRTS as required by changes in the SNR of the individual tones. The error detector detects phase errors in each received tone of the CRTS. The aggregator calculates an average aggregate phase error from all tones in the CRTS. The oscillator controls clocking of the transceiver. The oscillator is responsive to the average aggregate phase error to adjust a clock phase in a direction which reduces a phase error with a clock on the opposing transceiver.
摘要翻译：一种多音频收发器，包括：变换分量，音调选择器，误差检测器，聚合器和振荡器。变换分量将接收到的通信从时域变换到频域。音调选择器选择呈现提升的信噪比（SNR）的接收音调的子集作为时钟恢复音调集合（CRTS），并且根据需要通过改变信噪比（SNR）个人色调。误差检测器检测CRTS的每个接收音调中的相位误差。聚合器计算CRTS中所有音调的平均聚合相位误差。振荡器控制收发器的时钟。振荡器响应于平均聚合相位误差，以在相对的收发器上的时钟减小相位误差的方向上调整时钟相位。

7. 发明申请

US20100316102A1 Method and apparatus for clock recovery in XDSL transceivers 失效
标题翻译： XDSL收发器中时钟恢复的方法和装置
公开(公告)号：US20100316102A1
公开(公告)日：2010-12-16
申请号：US12802884
申请日：2010-06-15
申请人： Robert Ayrapetian , Qasem Aldrubi , Hossein Dehghan-Fard , Christopher Chow
发明人： Robert Ayrapetian , Qasem Aldrubi , Hossein Dehghan-Fard , Christopher Chow
IPC分类号： H04B1/38 , H04L25/00
CPC分类号： H04L27/2657 , H04L27/2676
摘要： A multi-tone transceiver including: a transform component, a tone selector, an error detector, an aggregator and an oscillator. The transform component transforms received communications from the time domain to the frequency domain. The tone selector selects a sub-set of the received tones which exhibit an elevated signal-to-noise ratio (SNR) as a clock recovery tone set (CRTS) and drops and add tones to the CRTS as required by changes in the SNR of the individual tones. The error detector detects phase errors in each received tone of the CRTS. The aggregator calculates an average aggregate phase error from all tones in the CRTS. The oscillator controls clocking of the transceiver. The oscillator is responsive to the average aggregate phase error to adjust a clock phase in a direction which reduces a phase error with a clock on the opposing transceiver.
摘要翻译：一种多音频收发器，包括：变换分量，音调选择器，误差检测器，聚合器和振荡器。变换分量将接收到的通信从时域变换到频域。音调选择器选择呈现提升的信噪比（SNR）的接收音调的子集作为时钟恢复音调集合（CRTS），并且根据需要通过改变信噪比（SNR）个人色调。误差检测器检测CRTS的每个接收音调中的相位误差。聚合器计算CRTS中所有音调的平均聚合相位误差。振荡器控制收发器的时钟。振荡器响应于平均聚合相位误差，以在相对的收发器上的时钟减小相位误差的方向上调整时钟相位。

8. 发明申请

US20070121660A1 Load balanced architecture of cascading of MxM Ethernet packet based switches that supports up to 4 levels of QoS 审中-公开
标题翻译：负载均衡的MxM以太网数据包交换机级联架构，支持多达4个QoS级别
公开(公告)号：US20070121660A1
公开(公告)日：2007-05-31
申请号：US11593807
申请日：2006-11-06
申请人： Robert Ayrapetian , Serob Douvalian
发明人： Robert Ayrapetian , Serob Douvalian
IPC分类号： H04L12/56
CPC分类号： H04L49/351 , H04L49/1515 , H04L49/205
摘要： A network switch is provided that includes a bank of input switches configured to receive variable length data packets; a bank of central switches configured to receive packets from the input switches in a distributed manner; and a bank of output switches configured to receive and output variable length packets from the bank of central switches.
摘要翻译：提供一种网络交换机，其包括被配置为接收可变长度数据分组的一组输入交换机; 一组中央交换机，被配置为以分布式方式从输入交换机接收分组; 以及一组输出开关，被配置为从中央交换机组接收和输出可变长度分组。

9. 发明授权

US07076002B1 Method and apparatus for symbol boundary synchronization 失效
标题翻译：符号边界同步的方法和装置
公开(公告)号：US07076002B1
公开(公告)日：2006-07-11
申请号：US10117823
申请日：2002-04-05
申请人： Fernando Ramirez-Mireles , Robert Ayrapetian , Dale Smith , Max Chien , Sam Heidari
发明人： Fernando Ramirez-Mireles , Robert Ayrapetian , Dale Smith , Max Chien , Sam Heidari
IPC分类号： H04L27/14 , H04L7/00 , H04J3/06 , H04J3/12
CPC分类号： H04L27/2662 , H04L27/2675
摘要： The apparatus for symbol boundary synchronization in one embodiment includes on the receive path of a multi-tone modem a window synchronizer, a converter and a symbol boundary component. The window synchronizer obtains windowed portions of the received datastream which includes symbols each expressed with a corresponding set of tones in a time domain. The windowed portions obtained in the training phase exhibit varying degrees of misalignment with the corresponding symbol boundaries. The window synchronizer is responsive to an alignment signal to obtain succeeding windowed portions of the incoming datastream aligned with the corresponding symbol boundaries therein. The converter couples to the window synchronizer to convert the set of tones from each windowed portion from the time domain to a frequency domain. The symbol boundary module couples to the converter to evaluate a phasor angle characteristic of selected tones from each windowed portion converted by the converter and to convert the phasor angle characteristic of the selected tones from a selected one of the windowed portions to the alignment signal to align the window synchronizer with the symbol boundaries in the received datastream. In an alternate embodiment of the invention the symbol boundary component couples to the window synchronizer to correlate sign values of the selected tones with a reference set and to output the alignment signal identifying the corresponding windowed portion which exhibits maximum correlation with the reference set to align the window synchronizer.
摘要翻译：在一个实施例中，用于符号边界同步的装置在多音调制解调器的接收路径上包括窗口同步器，转换器和符号边界部件。窗口同步器获得接收到的数据流的窗口化部分，其包括在时域中用相应的一组音调表示的符号。在训练阶段获得的窗口部分与相应的符号边界呈现不同程度的不对准。窗口同步器响应于对准信号以获得与其中的对应符号边界对准的输入数据流的后续窗口部分。转换器耦合到窗口同步器，以将来自每个窗口部分的音调集从时域转换到频域。符号边界模块耦合到转换器以评估来自由转换器转换的每个窗口部分的所选音调的相量角特性，并将所选择的音调的相量角特性从所选择的一个窗口部分转换为对准信号以对准窗口同步器与接收到的数据流中的符号边界。在本发明的替代实施例中，符号边界分量耦合到窗口同步器以将所选择的音调的符号值与参考集相关联，并输出识别与参考集合具有最大相关性的对应窗口部分的对准信号，以对准窗口同步器

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