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    • 5. 发明授权
    • Chip partitioning aid (CPA)-A structure for test pattern generation for
large logic networks
    • 芯片分配辅助(CPA) - 大型逻辑网络测试模式生成的结构
    • US4503386A
    • 1985-03-05
    • US370214
    • 1982-04-20
    • Sumit DasGuptaMatthew C. GrafRobert A. RasmussenThomas W. Williams
    • Sumit DasGuptaMatthew C. GrafRobert A. RasmussenThomas W. Williams
    • G06F11/22G01R31/28G01R31/3185G06F11/00H01L21/66H01L21/822H01L27/04
    • G01R31/318583H01L2924/0002
    • Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly. One method, full CPA, offers the ability to apply these tests to all full CPA chips on the multichip package simultaneously or in unison, thus reducing manufacturing tester time. An additional benefit is the ease of testing intercomponent connections.
    • 公开了以电路和测试方法或方法的形式的设计学科或方法,其消除现有技术的问题,并且允许测试包含在或内部的多个互连芯片中的每个单独芯片和芯片间连接 高密度包装结构。 该测试是在不需要和利用具有精密探针和高精度步骤和重复机构的测试设备的情况下完成的。 CPA是一种方法和电路设计规则,其中随之而来,将导致可测试的多芯片封装,因为每个逻辑组件都是可测试的,并且设计本质上是同步的。 CPA学科能够通过利用芯片或功能岛周边的移位寄存器锁存来实现这一点。 这些锁存器用于间接地观察和/或控制同步网络,在许多方面复制了在组装的较低子组件级别下生成测试的卡住的故障测试环境。 一种完全CPA的方法可以同时或一致地将这些测试应用于多芯片封装上的所有CPA芯片,从而减少制造测试人员的时间。 另外的好处是测试组件间连接的便利性。