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1. 发明授权

US5461642A Discrete time control loop method and apparatus for clocking data in an asynchronous channel 失效
标题翻译：用于在异步通道中对数据进行计时的离散时间控制环路方法和装置
公开(公告)号：US5461642A
公开(公告)日：1995-10-24
申请号：US401055
申请日：1995-03-08
申请人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
发明人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/10 , G11B20/14 , H04N5/932 , H04N5/76 , G11B5/09
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H04N5/932
摘要： A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.
摘要翻译：一种数字数据时钟控制回路，用于重建记录通道中的异步数据时钟。离散时间控制环（DTCL）实现适用于单片数字实施例，并且不使用模拟组件，在没有硬件振荡器的情况下以广泛变化的时钟速率提供稳定的操作。 DTCL还可以提供时钟功能，以在异步数据采样系统中恢复同步采样。

2. 发明授权

US5315284A Asynchronous digital threshold detector for a digital data storage channel 失效
标题翻译：用于数字数据存储通道的异步数字阈值检测器
公开(公告)号：US5315284A
公开(公告)日：1994-05-24
申请号：US73921
申请日：1993-06-07
申请人： Steven R. Bentley , Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
发明人： Steven R. Bentley , Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/14 , G11B20/10 , H03K5/1536 , G05B1/03 , G06F7/02 , H03K5/153
CPC分类号： H03K5/1536 , G11B20/10009
摘要： A zero-crossing detector for asynchronous detection of threshold transitions in a digitally sampled signal waveform. The Asynchronous Digital Threshold Detector (ADTD) receives a digitized self-clocking data readback waveform and provides the relative location of a zero-crossing within the sample period where it occurs. The digital output, which is useful for recovering data and clock signals, is in a digital form that can be used directly by a certain class of asynchronous digital phase detector systems. The ADTD is entirely digital and can be embodied in a low power configuration using CMOS technology.
摘要翻译：用于异步检测数字采样信号波形中的阈值转换的过零检测器。异步数字阈值检测器（ADTD）接收数字化的自时钟数据回读波形，并在发生的采样周期内提供过零点的相对位置。用于恢复数据和时钟信号的数字输出是数字形式，可以由某种类型的异步数字相位检测器系统直接使用。 ADTD是完全数字化的，可以使用CMOS技术实现低功耗配置。

3. 发明授权

US5461638A Discrete time control loop method for clocking data in an asynchronous channel 失效
标题翻译：用于在异步通道中对数据进行时钟的离散时间控制环路方法
公开(公告)号：US5461638A
公开(公告)日：1995-10-24
申请号：US200608
申请日：1994-02-23
申请人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
发明人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/10 , G11B20/14 , H04N5/932 , H04L7/00
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H04N5/932
摘要： A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.
摘要翻译：一种数字数据时钟控制回路，用于重建记录通道中的异步数据时钟。离散时间控制环（DTCL）实现适用于单片数字实施例，并且不使用模拟组件，在没有硬件振荡器的情况下以广泛变化的时钟速率提供稳定的操作。 DTCL还可以提供时钟功能，以在异步数据采样系统中恢复同步采样。

4. 发明授权

US5295128A Clock controller employing a discrete time control loop method for clocking data in an asynchronous channel 失效
标题翻译：时钟控制器采用离散时间控制环路方法，用于在异步通道中对数据进行计时
公开(公告)号：US5295128A
公开(公告)日：1994-03-15
申请号：US967588
申请日：1992-10-28
申请人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
发明人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/10 , G11B20/14 , H04N5/932 , H04N5/76 , G11B5/09
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H04N5/932
摘要： A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.
摘要翻译：一种数字数据时钟控制回路，用于重建记录通道中的异步数据时钟。离散时间控制环（DTCL）实现适用于单片数字实施例，并且不使用模拟组件，在没有硬件振荡器的情况下以广泛变化的时钟速率提供稳定的操作。 DTCL还可以提供时钟功能，以在异步数据采样系统中恢复同步采样。

5. 发明授权

US5293369A Asynchronous sampling digital detector system for magnetic and optical recording channels 失效
标题翻译：用于磁光记录通道的异步采样数字检测系统
公开(公告)号：US5293369A
公开(公告)日：1994-03-08
申请号：US967669
申请日：1992-10-28
申请人： Constantin M. Melas , Pantas Sutardja
发明人： Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/10 , G11B5/09 , G06F7/38 , H03D1/22 , H03K5/153 , H04N5/76
CPC分类号： G11B20/10527 , G11B20/10009
摘要： A variable sampling-rate digital channel phase detector for reading synchronous data recordings from magnetic or optical media. All-digital implementation allows multiplexing of several parallel channels on a single monolithic chip for tape storage systems or other magnetic or optical data storage systems. The ASDD channel signal processing is entirely digital and includes A/D converter, digital filter and equalizer, digital differentiator and zero-crossing detector, peak amplitude estimator, zero-crossing qualifier and zero-crossing position (phase) estimator. The ASDD input is an analog waveform and the output includes two flags for qualified negative and positive waveform threshold-crossings and a digital signal encoding a waveform threshold-crossing position within the current sampling clock interval. The ASDD operates over a wide continuous range of channel data rates and provides accurate phase detection at relatively low sampling rates. It is suitable for monolithic CMOS implementation, which provides low power dissipation and small size.
摘要翻译：一种可变采样率数字通道相位检测器，用于从磁介质或光介质读取同步数据记录。全数字实现允许在用于磁带存储系统或其他磁或光数据存储系统的单个单片芯片上复用多个并行通道。 ASDD通道信号处理完全是数字的，包括A / D转换器，数字滤波器和均衡器，数字微分器和过零检测器，峰值幅度估计器，过零限位器和过零位置（相位）估计器。 ASDD输入是模拟波形，输出包括两个用于合格的负和正波形阈值交叉的标志，以及编码当前采样时钟间隔内波形阈值交叉位置的数字信号。 ASDD在广泛的通道数据速率范围内工作，并以相对低的采样率提供精确的相位检测。它适用于单片CMOS实现，提供低功耗和小尺寸。

6. 发明授权

US5535187A High capacity run-length-limited coding system employing asymmetric and even-spaced codes 失效
标题翻译：高容量游程长度限制编码系统采用不对称和偶数间隔码
公开(公告)号：US5535187A
公开(公告)日：1996-07-09
申请号：US167104
申请日：1993-12-15
申请人： Constantin M. Melas , Daniel Rugar , Pantas Sutardja , Roger W. Wood
发明人： Constantin M. Melas , Daniel Rugar , Pantas Sutardja , Roger W. Wood
IPC分类号： G06T9/00 , G11B20/14 , G11B5/09
CPC分类号： G11B20/1426 , G06T9/005
摘要： A system for encoding and decoding binary data in a data transmission system, such as a magnetic or optical data storage channel. The encoding process is implemented as a two-step RLL coding procedure wherein the original user bit data are first encoded as an asymmetric RLL code signal at a reduced clock rate and then translated to a second even-spaced RLL code signal suitable for recording to a data storage medium at a full-speed clock rate. The system also provides for recovering suitable even-spaced RLL codes recorded at a full-speed clock rate, translating the recovered even-spaced RLL code signal to an asymmetric RLL code signal at a reduced clock rate, and then decoding the asymmetric RLL code signal to recover the original user bit data. A preferred embodiment uses a rate 2/5 (2, 16, 2) even-spaced RLL code at a full-speed clock rate and a rate 4/5 (0,7; 1,8) asymmetric RLL code at a half-speed clock rate. The rate 4/5 asymmetric RLL code has a high capacity and the rate 2/5 even-spaced RLL code has a wide detection window. The intercode translation procedure requires only simple time-delay circuitry.
摘要翻译：用于在诸如磁或光数据存储通道的数据传输系统中对二进制数据进行编码和解码的系统。编码过程被实现为两步RLL编码过程，其中原始用户比特数据首先以降低的时钟速率编码为非对称RLL码信号，然后被转换为适合于记录到第二偶数RLL码信号数据存储介质以全速时钟速率。该系统还提供恢复以全速时钟速率记录的合适的均匀间隔的RLL码，将恢复的均匀间隔的RLL码信号以降低的时钟速率转换为非对称RLL码信号，然后解码非对称RLL码信号恢复原始用户比特数据。优选实施例以全速时钟速率和半衰期的速率4/5（0,7; 1,8）非对称RLL码使用速率2/5（2,16,2）均匀间隔的RLL码，速度时钟速率。速率4/5非对称RLL码具有高容量，速率2/5偶数间隔的RLL码具有宽的检测窗口。码间转换过程只需要简单的延时电路。

7. 发明授权

US4804959A Method and apparatus using multiple codes to increase storage capacity 失效
标题翻译：使用多个代码来增加存储容量的方法和装置
公开(公告)号：US4804959A
公开(公告)日：1989-02-14
申请号：US119010
申请日：1987-11-10
申请人： Tarek Makansi , Constantin M. Melas , Arvind M. Patel , Steven H. Souther
发明人： Tarek Makansi , Constantin M. Melas , Arvind M. Patel , Steven H. Souther
IPC分类号： G11B5/09 , G11B5/012 , G11B20/10 , G11B20/14 , H03M7/00
CPC分类号： G11B5/012 , G11B20/10
摘要： To increase storage capacity of a disk storage device, the recording surface of the device is partitioned into a plurality of concentric recording bands, data to be recorded on respective bands are encoded using different run-length-limited codes with the code rate of each band being higher than the adjacent inner band.

8. 发明授权

US5461631A Method for bit resynchronization of code-constrained sequences 失效
标题翻译：代码约束序列的位重新同步的方法
公开(公告)号：US5461631A
公开(公告)日：1995-10-24
申请号：US990911
申请日：1992-12-15
申请人： Miguel M. Blaum , Jehoshua Bruck , Constantin M. Melas
发明人： Miguel M. Blaum , Jehoshua Bruck , Constantin M. Melas
IPC分类号： G06F11/00 , H03M13/31 , H03M13/33
CPC分类号： G06F11/0763 , H03M13/31 , H03M13/33
摘要： A method is disclosed for recovery from synchronization errors caused by deletions and/or insertions of symbols in the presence of errors that alter the symbols in any code constrained binary record. The method initially divides the sequence of data into equal size blocks before appending a binary sync sequence at the end of each block not encountered in the block. Then, the blocks are resynchronized by first determining the size of any symbol insertions and/or deletions that have occurred. Then, scanning for the sync sequence starting at the presumed end of the data field of the current block so as to determine the offset of the sync sequence with respect to that specific location. After this location of the insertions and/or deletions has been determined, a corresponding number of symbols can be added or deleted from the middle of the block according to the offset determined by the present method.
摘要翻译：公开了一种用于在存在可改变任何代码受限二进制记录中的符号的错误的情况下由符号的删除和/或插入引起的同步错误的恢复方法。该方法最初将数据序列划分成相等大小的块，然后在块中未遇到的每个块的末尾追加二进制同步序列。然后，通过首先确定发生的任何符号插入和/或缺失的大小来重新同步块。然后，从当前块的数据字段的假设结束开始扫描同步序列，以便确定同步序列相对于该特定位置的偏移量。在确定了插入和/或删除的该位置之后，可以根据由本方法确定的偏移量从块的中间添加或删除相应数量的符号。

9. 发明授权

US4417245A Digital space division exchange 失效
标题翻译：数字空间交换
公开(公告)号：US4417245A
公开(公告)日：1983-11-22
申请号：US298705
申请日：1981-09-02
申请人： Constantin M. Melas , Michael A. Patten
发明人： Constantin M. Melas , Michael A. Patten
IPC分类号： H04Q3/545 , H04Q3/68 , H04Q9/00 , H04Q3/00
CPC分类号： H04Q3/68 , H04Q3/5455
摘要： A switching network is comprised of a plurality of identical chips and a network (control) processor. Each of the chips is a novel intelligent switch and includes both a cross point array as well as apparatus to control the cross point array in response to a set of multi bit commands or to formulate a response to a query concerning status of the switching array. The number of command lines connecting network (control) processor to each of the array chips may be as few as two. The cross point array includes a cross point device (switch) for each inlet-outlet combination. The total number of cross points in the network is lower than that dictated by a CLOS network.
摘要翻译：交换网络由多个相同的芯片和网络（控制）处理器组成。每个芯片是新颖的智能开关，并且包括交叉点阵列以及响应于一组多位命令来控制交叉点阵列的装置，或者对关于开关阵列的状态的查询制定响应。将网络（控制）处理器连接到每个阵列芯片的命令行数可以少至两个。交叉点阵列包括用于每个入口 - 出口组合的交叉点装置（开关）。网络中的交叉点总数低于CLOS网络规定的交叉点总数。

10. 发明授权

US4417244A Automatic path rearrangement for blocking switching matrix 失效
标题翻译：自动路径重排用于阻塞切换矩阵
公开(公告)号：US4417244A
公开(公告)日：1983-11-22
申请号：US298398
申请日：1981-09-01
申请人： Constantin M. Melas
发明人： Constantin M. Melas
IPC分类号： H04Q3/545 , H04Q3/52 , H04Q3/64 , H04Q3/68 , H04Q9/00
CPC分类号： H04Q3/68 , H04Q2213/1334
摘要： A method for rearranging a three stage (primary, intermediate, tertiary) switching network to permit data or digitized voice signals to be transmitted from any given primary outlet to any given tertiary inlet. The intermediate stage has fewer inlets than the number of primary stage outlets and fewer outlets than the number of tertiary stage inlets, making the network a conditionally blocking one. Two call rearranging buses are provided to assure that each signal path being rearranged is maintained to prevent data transmission dropout. Primary to intermediate and intermediate to tertiary paths are rearranged one at a time using the call rearranging buses to move free primary and tertiary links to a single intermediate matrix.
摘要翻译：一种用于重新布置三级（主，中，三级）交换网络以允许数据或数字化语音信号从任何给定主出口传输到任何给定的三级入口的方法。中级阶段比初级阶段出口数量少，出口数量少于三级入口数量，使网络有条件地阻塞。提供两个呼叫重排总线以确保重新排列的每个信号路径被保持以防止数据传输丢失。主要到中间和中间到第三路径每次重新排列一次，使用呼叫重排总线将空闲的第一和第三链路移动到单个中间矩阵。

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