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1. 发明授权

US5535187A High capacity run-length-limited coding system employing asymmetric and even-spaced codes 失效
标题翻译：高容量游程长度限制编码系统采用不对称和偶数间隔码
公开(公告)号：US5535187A
公开(公告)日：1996-07-09
申请号：US167104
申请日：1993-12-15
申请人： Constantin M. Melas , Daniel Rugar , Pantas Sutardja , Roger W. Wood
发明人： Constantin M. Melas , Daniel Rugar , Pantas Sutardja , Roger W. Wood
IPC分类号： G06T9/00 , G11B20/14 , G11B5/09
CPC分类号： G11B20/1426 , G06T9/005
摘要： A system for encoding and decoding binary data in a data transmission system, such as a magnetic or optical data storage channel. The encoding process is implemented as a two-step RLL coding procedure wherein the original user bit data are first encoded as an asymmetric RLL code signal at a reduced clock rate and then translated to a second even-spaced RLL code signal suitable for recording to a data storage medium at a full-speed clock rate. The system also provides for recovering suitable even-spaced RLL codes recorded at a full-speed clock rate, translating the recovered even-spaced RLL code signal to an asymmetric RLL code signal at a reduced clock rate, and then decoding the asymmetric RLL code signal to recover the original user bit data. A preferred embodiment uses a rate 2/5 (2, 16, 2) even-spaced RLL code at a full-speed clock rate and a rate 4/5 (0,7; 1,8) asymmetric RLL code at a half-speed clock rate. The rate 4/5 asymmetric RLL code has a high capacity and the rate 2/5 even-spaced RLL code has a wide detection window. The intercode translation procedure requires only simple time-delay circuitry.
摘要翻译：用于在诸如磁或光数据存储通道的数据传输系统中对二进制数据进行编码和解码的系统。编码过程被实现为两步RLL编码过程，其中原始用户比特数据首先以降低的时钟速率编码为非对称RLL码信号，然后被转换为适合于记录到第二偶数RLL码信号数据存储介质以全速时钟速率。该系统还提供恢复以全速时钟速率记录的合适的均匀间隔的RLL码，将恢复的均匀间隔的RLL码信号以降低的时钟速率转换为非对称RLL码信号，然后解码非对称RLL码信号恢复原始用户比特数据。优选实施例以全速时钟速率和半衰期的速率4/5（0,7; 1,8）非对称RLL码使用速率2/5（2,16,2）均匀间隔的RLL码，速度时钟速率。速率4/5非对称RLL码具有高容量，速率2/5偶数间隔的RLL码具有宽的检测窗口。码间转换过程只需要简单的延时电路。

2. 发明授权

US5461638A Discrete time control loop method for clocking data in an asynchronous channel 失效
标题翻译：用于在异步通道中对数据进行时钟的离散时间控制环路方法
公开(公告)号：US5461638A
公开(公告)日：1995-10-24
申请号：US200608
申请日：1994-02-23
申请人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
发明人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/10 , G11B20/14 , H04N5/932 , H04L7/00
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H04N5/932
摘要： A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.
摘要翻译：一种数字数据时钟控制回路，用于重建记录通道中的异步数据时钟。离散时间控制环（DTCL）实现适用于单片数字实施例，并且不使用模拟组件，在没有硬件振荡器的情况下以广泛变化的时钟速率提供稳定的操作。 DTCL还可以提供时钟功能，以在异步数据采样系统中恢复同步采样。

3. 发明授权

US5461642A Discrete time control loop method and apparatus for clocking data in an asynchronous channel 失效
标题翻译：用于在异步通道中对数据进行计时的离散时间控制环路方法和装置
公开(公告)号：US5461642A
公开(公告)日：1995-10-24
申请号：US401055
申请日：1995-03-08
申请人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
发明人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/10 , G11B20/14 , H04N5/932 , H04N5/76 , G11B5/09
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H04N5/932
摘要： A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.
摘要翻译：一种数字数据时钟控制回路，用于重建记录通道中的异步数据时钟。离散时间控制环（DTCL）实现适用于单片数字实施例，并且不使用模拟组件，在没有硬件振荡器的情况下以广泛变化的时钟速率提供稳定的操作。 DTCL还可以提供时钟功能，以在异步数据采样系统中恢复同步采样。

4. 发明授权

US5315284A Asynchronous digital threshold detector for a digital data storage channel 失效
标题翻译：用于数字数据存储通道的异步数字阈值检测器
公开(公告)号：US5315284A
公开(公告)日：1994-05-24
申请号：US73921
申请日：1993-06-07
申请人： Steven R. Bentley , Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
发明人： Steven R. Bentley , Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/14 , G11B20/10 , H03K5/1536 , G05B1/03 , G06F7/02 , H03K5/153
CPC分类号： H03K5/1536 , G11B20/10009
摘要： A zero-crossing detector for asynchronous detection of threshold transitions in a digitally sampled signal waveform. The Asynchronous Digital Threshold Detector (ADTD) receives a digitized self-clocking data readback waveform and provides the relative location of a zero-crossing within the sample period where it occurs. The digital output, which is useful for recovering data and clock signals, is in a digital form that can be used directly by a certain class of asynchronous digital phase detector systems. The ADTD is entirely digital and can be embodied in a low power configuration using CMOS technology.
摘要翻译：用于异步检测数字采样信号波形中的阈值转换的过零检测器。异步数字阈值检测器（ADTD）接收数字化的自时钟数据回读波形，并在发生的采样周期内提供过零点的相对位置。用于恢复数据和时钟信号的数字输出是数字形式，可以由某种类型的异步数字相位检测器系统直接使用。 ADTD是完全数字化的，可以使用CMOS技术实现低功耗配置。

5. 发明授权

US5293369A Asynchronous sampling digital detector system for magnetic and optical recording channels 失效
标题翻译：用于磁光记录通道的异步采样数字检测系统
公开(公告)号：US5293369A
公开(公告)日：1994-03-08
申请号：US967669
申请日：1992-10-28
申请人： Constantin M. Melas , Pantas Sutardja
发明人： Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/10 , G11B5/09 , G06F7/38 , H03D1/22 , H03K5/153 , H04N5/76
CPC分类号： G11B20/10527 , G11B20/10009
摘要： A variable sampling-rate digital channel phase detector for reading synchronous data recordings from magnetic or optical media. All-digital implementation allows multiplexing of several parallel channels on a single monolithic chip for tape storage systems or other magnetic or optical data storage systems. The ASDD channel signal processing is entirely digital and includes A/D converter, digital filter and equalizer, digital differentiator and zero-crossing detector, peak amplitude estimator, zero-crossing qualifier and zero-crossing position (phase) estimator. The ASDD input is an analog waveform and the output includes two flags for qualified negative and positive waveform threshold-crossings and a digital signal encoding a waveform threshold-crossing position within the current sampling clock interval. The ASDD operates over a wide continuous range of channel data rates and provides accurate phase detection at relatively low sampling rates. It is suitable for monolithic CMOS implementation, which provides low power dissipation and small size.
摘要翻译：一种可变采样率数字通道相位检测器，用于从磁介质或光介质读取同步数据记录。全数字实现允许在用于磁带存储系统或其他磁或光数据存储系统的单个单片芯片上复用多个并行通道。 ASDD通道信号处理完全是数字的，包括A / D转换器，数字滤波器和均衡器，数字微分器和过零检测器，峰值幅度估计器，过零限位器和过零位置（相位）估计器。 ASDD输入是模拟波形，输出包括两个用于合格的负和正波形阈值交叉的标志，以及编码当前采样时钟间隔内波形阈值交叉位置的数字信号。 ASDD在广泛的通道数据速率范围内工作，并以相对低的采样率提供精确的相位检测。它适用于单片CMOS实现，提供低功耗和小尺寸。

6. 发明授权

US5295128A Clock controller employing a discrete time control loop method for clocking data in an asynchronous channel 失效
标题翻译：时钟控制器采用离散时间控制环路方法，用于在异步通道中对数据进行计时
公开(公告)号：US5295128A
公开(公告)日：1994-03-15
申请号：US967588
申请日：1992-10-28
申请人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
发明人： Robert A. Hutchins , Constantin M. Melas , Pantas Sutardja
IPC分类号： G11B20/10 , G11B20/14 , H04N5/932 , H04N5/76 , G11B5/09
CPC分类号： G11B20/10037 , G11B20/10009 , G11B20/1403 , H04N5/932
摘要： A digital data clock control loop for reconstructing the asynchronous data clock in a recording channel. The Discrete Time Control Loop (DTCL) implementation is suitable for monolithic digital embodiment and uses no analog components, providing stable operation at widely varying clock rates without hardware oscillators. The DTCL also can supply the clocking function to recover synchronous samples in an asynchronous data sampling system.
摘要翻译：一种数字数据时钟控制回路，用于重建记录通道中的异步数据时钟。离散时间控制环（DTCL）实现适用于单片数字实施例，并且不使用模拟组件，在没有硬件振荡器的情况下以广泛变化的时钟速率提供稳定的操作。 DTCL还可以提供时钟功能，以在异步数据采样系统中恢复同步采样。

7. 发明授权

US09445475B1 Buck regulator for LED lighting color mixing and/or current compensation 有权
标题翻译：降压调节器用于LED照明混色和/或电流补偿
公开(公告)号：US09445475B1
公开(公告)日：2016-09-13
申请号：US13551118
申请日：2012-07-17
申请人： Sehat Sutardja , Pantas Sutardja , Wanfeng Zhang
发明人： Sehat Sutardja , Pantas Sutardja , Wanfeng Zhang
IPC分类号： H05B33/08
CPC分类号： H05B33/0857 , H05B33/0824 , H05B33/0827 , H05B33/0845
摘要： A light emitting diode (LED) lighting system includes a first string of first LEDs emitting light having a first color. A second string of second LEDs emits light having a second color and connected in series with the first string of first LEDs; A first switch and a second switch are connected in series. A regulator module is configured to modulate the first switch and the second switch to provide a desired current ratio. The desired current ratio corresponds to a ratio of a first current through the first string of first LEDs to a second current through the second string of second LEDs.
摘要翻译：发光二极管（LED）照明系统包括发射具有第一颜色的光的第一串第一LED。第二串第二LED发射具有第二颜色并与第一串第一LED串联连接的光; 第一开关和第二开关串联连接。调节器模块被配置为调制第一开关和第二开关以提供期望的电流比。期望的电流比对应于通过第一串第一LED的第一电流与通过第二LED的第二串的第二电流的比率。

8. 发明授权

US08887005B2 Caching system with removable memory card 有权
标题翻译：具有可移动存储卡的缓存系统
公开(公告)号：US08887005B2
公开(公告)日：2014-11-11
申请号：US13596489
申请日：2012-08-28
申请人： Pantas Sutardja , Abhijeet P. Gole
发明人： Pantas Sutardja , Abhijeet P. Gole
IPC分类号： G06F11/00 , G06F11/14 , G06F12/08 , G06F11/07 , G06F11/16 , G06F11/20
CPC分类号： G06F12/0868 , G06F11/073 , G06F11/076 , G06F11/1428 , G06F11/1666 , G06F11/20
摘要： Systems, methods, and other embodiments associated with optimizing the use of replaceable memory cards and onboard memory as storage for data in cache are described. According to one embodiment, an apparatus includes a cache space manager configured to cause a cache processor to store data of a removable memory card of a memory device to an onboard memory of the memory device. The apparatus also includes an error rate monitor configured to monitor operating parameters of the removable memory card and to activate a cache processor to store the data from the removable memory card to the onboard memory when the operating parameters meet predetermined criteria.
摘要翻译：描述了与优化可替换存储卡和板载存储器的使用相关联的系统，方法和其他实施例，作为高速缓存中的数据的存储。根据一个实施例，一种装置包括高速缓存空间管理器，其被配置为使高速缓存处理器将存储器设备的可移动存储卡的数据存储到存储器设备的板上存储器。该装置还包括错误率监视器，其被配置为监视可移动存储卡的操作参数，并且当操作参数满足预定标准时激活高速缓存处理器以将数据从可移动存储卡存储到板载存储器。

9. 发明授权

US08693300B1 Write PLL for optical disc labeling applications 失效
标题翻译：为光盘标签应用编写PLL
公开(公告)号：US08693300B1
公开(公告)日：2014-04-08
申请号：US13208047
申请日：2011-08-11
申请人： Pantas Sutardja , Christopher Painter
发明人： Pantas Sutardja , Christopher Painter
IPC分类号： G11B7/00
CPC分类号： G11B7/0037 , G11B2007/0016
摘要： A system includes a position detection module configured to detect at least a first position indicator and a second position indicator corresponding to a label side of an optical disc. A write clock adjustment module is configured to determine a number of cycles of a write clock that occur between the first position indicator and the second position indicator, determine a difference between the number of cycles of the write clock and a desired number of cycles of the write clock, and adjust a frequency of the write clock based on the difference.
摘要翻译：系统包括位置检测模块，其被配置为检测至少第一位置指示器和对应于光盘的标签侧的第二位置指示器。写时钟调整模块被配置为确定在第一位置指示符和第二位置指示符之间发生的写入时钟的周期数，确定写入时钟的周期数与期望的周期数之间的差异写时钟，并根据差异来调整写时钟的频率。

10. 发明授权

US08493028B2 Power management circuit for rechargeable battery stack 有权
标题翻译：可充电电池堆的电源管理电路
公开(公告)号：US08493028B2
公开(公告)日：2013-07-23
申请号：US12725683
申请日：2010-03-17
申请人： Pantas Sutardja
发明人： Pantas Sutardja
IPC分类号： H02J7/00
CPC分类号： H02J7/0014 , Y02T10/7055
摘要： A charge-balancing system includes N circuits and a control module, where N is an integer greater than or equal to 1. Each of the N circuits includes first and second switches connected in series and an inductance having a first end connected between the first and second switches. The control module outputs control signals to control the first and second switches. A second end of the inductance of a first one of the N circuits is connected between two cells of a first pair of 2N series-connected cells of a battery stack. The first and second switches of the first one of the N circuits are connected in parallel to the first pair of 2N series-connected cells.
摘要翻译：电荷平衡系统包括N个电路和一个控制模块，其中N是大于或等于1的整数。N个电路中的每一个包括串联连接的第一和第二开关，以及电感，其第一端连接在第一和第二个开关控制模块输出控制信号以控制第一和第二开关。 N个电路中的第一个电路的电感的第二端连接在电池堆叠的第一对2N个串联连接的单元的两个单元之间。 N个电路中的第一个的第一和第二开关与第一对2N个串联的单元并联连接。

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