专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06237104B1 Method and a related circuit for adjusting the duration of a synchronization signal ATD for timing the access to a non-volatile memory 有权
标题翻译：方法和相关电路，用于调整同步信号ATD的持续时间，用于定时访问非易失性存储器
公开(公告)号：US06237104B1
公开(公告)日：2001-05-22
申请号：US09222070
申请日：1998-12-29
申请人： Rino Micheloni , Giovanni Campardo , Stefano Commodaro , Guido Lomazzi
发明人： Rino Micheloni , Giovanni Campardo , Stefano Commodaro , Guido Lomazzi
IPC分类号： G06F1200
CPC分类号： G11C8/18 , G11C16/32
摘要： A method and related circuit for adjusting the duration of a pulse synchronization signal for the reading phase of memory cells in electronic memory devices which are integrated on semiconductors are discussed. The pulse synchronization signal is produced by a pulse generator when it detects a logical state commutation on at least one input terminal of a plurality of addressing input terminals of the memory cells. The method produces a logical sum between the signal produced by the generator and a pulse signal having a predetermined duration. The logical sum is used to start up the reading phase.
摘要翻译：讨论了用于调整集成在半导体上的电子存储器件中的存储器单元的读取阶段的脉冲同步信号的持续时间的方法和相关电路。当脉冲同步信号检测到存储器单元的多个寻址输入端的至少一个输入端上的逻辑状态换向时，脉冲同步信号由脉冲发生器产生。该方法产生由发生器产生的信号与具有预定持续时间的脉冲信号之间的逻辑和。逻辑和用于启动读取阶段。

2. 发明授权

US6128225A Method and circuit for reading low-supply-voltage nonvolatile memory cells 失效
标题翻译：读取低电压 - 非易失性存储单元的方法和电路
公开(公告)号：US6128225A
公开(公告)日：2000-10-03
申请号：US879017
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
发明人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
IPC分类号： G11C16/06 , G11C16/28 , G11C16/02
CPC分类号： G11C16/28
摘要： The read circuit has an array branch connected to an array cell, and a reference branch connected to a reference cell; the array branch presents an array load transistor interposed between a supply line and the array cell, and the reference branch presents a reference load transistor interposed between the supply line and the reference cell; and the array and reference load transistors form a current mirror wherein the array load transistor is diode-connected and presents a first predetermined channel width/length ratio, and the reference load transistor presents a second predetermined channel width/length ratio N times greater than the first ratio, so that the current flowing in the array cell is supplied, amplified, to the reference branch.
摘要翻译：读取电路具有连接到阵列单元的阵列分支和连接到参考单元的参考分支; 阵列分支呈现插入在电源线和阵列单元之间的阵列负载晶体管，参考支路呈现插在电源线和参考单元之间的基准负载晶体管; 并且阵列和参考负载晶体管形成电流镜，其中阵列负载晶体管是二极管连接的并且呈现第一预定沟道宽度/长度比，并且参考负载晶体管呈现第二预定沟道宽/长比N 使得流过阵列单元的电流被提供，放大到参考分支。

3. 发明授权

US5903498A Low-supply-voltage nonvolatile memory device with voltage boosting 失效
标题翻译：具有升压功能的低电压非易失性存储器件
公开(公告)号：US5903498A
公开(公告)日：1999-05-11
申请号：US877927
申请日：1997-06-18
申请人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
发明人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
IPC分类号： G11C16/08 , G11C7/00
CPC分类号： G11C16/08
摘要： The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.
摘要翻译：存储器件具有多个本地升压电路，每个局部升压电路各自连接到存储器阵列的扇区，并且每个具有控制电路，至少相应的升压电容器和相应的驱动电路。每个驱动电路仅在读取模式下被启用，在接收到地址转换检测信号和扇区使能信号时，用于读取形成相应扇区的一部分的存储器单元。升压电压仅提供给行解码器的最终反相器。钳位二极管限制升压电压，以防止连接到非寻址字线的最终逆变器的PMOS晶体管的不期望的直接偏置。因此，过电压仅在必要时在当地提供。

4. 发明授权

US06351413B1 Nonvolatile memory device, in particular a flash-EEPROM 失效
标题翻译：非易失性存储器件，特别是闪存EEPROM
公开(公告)号：US06351413B1
公开(公告)日：2002-02-26
申请号：US09552945
申请日：2000-04-20
申请人： Rino Micheloni , Giovanni Campardo , Stefano Commodaro , Francesco Farina
发明人： Rino Micheloni , Giovanni Campardo , Stefano Commodaro , Francesco Farina
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C5/025 , G11C7/18 , G11C8/10
摘要： The memory array comprises a plurality of cells, grouped together in sectors and arranged in sector rows and columns, and has both hierarchical row decoding and hierarchical column decoding. Global word lines are connected to at least two word lines in each sector, through local row decoders; global bit lines are connected to at least two local bit lines in each sector, through local column decoders. The global column decoder is arranged in the center of the memory array, and separates from each other an upper half and a lower half of the memory array. Sense amplifiers are also arranged in the middle of the array, thus saving space. This architecture also provides lesser stress of the cells, better reliability, and better production performance. In addition, each sector is completely disconnected from the remaining sectors, and only the faulty row or column of a single sector should be doubled.
摘要翻译：存储器阵列包括多个单元，分组在扇区中并以扇区行和列排列，并且具有分级行解码和分层列解码。全局字线通过局部行解码器连接到每个扇区中的至少两个字线; 全局位线通过本地列解码器连接到每个扇区中的至少两个局部位线。全局列解码器被布置在存储器阵列的中心，并且彼此分离存储器阵列的上半部和下半部。感应放大器也布置在阵列的中间，从而节省空间。该架构还提供更小的电池应力，更好的可靠性和更好的生产性能。此外，每个扇区与其余扇区完全断开连接，只有单个扇区的故障行或列应该加倍。

5. 发明授权

US6018255A Line decoder for memory devices 失效
公开(公告)号：US6018255A
公开(公告)日：2000-01-25
申请号：US862563
申请日：1997-05-23
申请人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
发明人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
IPC分类号： G11C8/10 , G11C16/12 , H03K19/082
CPC分类号： G11C8/10 , G11C16/12
摘要： The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.

6. 发明授权

US5946238A Single-cell reference signal generating circuit for reading nonvolatile memory 失效
标题翻译：用于读取非易失性存储器的单单元参考信号发生电路
公开(公告)号：US5946238A
公开(公告)日：1999-08-31
申请号：US877066
申请日：1997-06-17
申请人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
发明人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
IPC分类号： G11C16/28 , G11C16/06
CPC分类号： G11C16/28
摘要： A nonvolatile memory having a memory array including a plurality of data cells and a read circuit. The read circuit includes a plurality of sense amplifiers, each connected to a respective array branch to be connected to the data cells. The nonvolatile memory also includes a reference generating circuit including a single reference cell arranged outside the memory array and generates a reference signal. The reference generating circuit includes a plurality of reference branches, each connected to a respective sense amplifier, and circuits interposed between the reference cell and the reference branches to supply the reference branches with a signal based on the reference signal.
摘要翻译：一种具有包括多个数据单元和读取电路的存储器阵列的非易失性存储器。读取电路包括多个读出放大器，每个读出放大器连接到要连接到数据单元的相应的阵列分支。非易失性存储器还包括参考产生电路，其包括布置在存储器阵列外部的单个参考单元并产生参考信号。参考产生电路包括多个参考分支，每个参考分支连接到相应的读出放大器，以及插入参考单元和参考分支之间的电路，以基于参考信号为参考分支提供信号。

7. 发明授权

US6094073A Line decoder for memory devices 有权
标题翻译：用于存储器件的线路解码器
公开(公告)号：US6094073A
公开(公告)日：2000-07-25
申请号：US432642
申请日：1999-11-02
申请人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
发明人： Giovanni Campardo , Rino Micheloni , Stefano Commodaro
IPC分类号： G11C8/10 , G11C16/12 , H03K19/082
CPC分类号： G11C8/10 , G11C16/12
摘要： The row decoder includes a predecoding stage supplied with row addresses and generating predecoding signals; and a final decoding stage, which, on the basis of the predecoding signals, drives the individual rows in the array. The predecoding stage includes a number of predecoding circuits presenting two parallel signal paths: a low-voltage path used in read mode, and a high-voltage path used in programming mode. A CMOS switch separates the two paths, is driven by high voltage via a voltage shifter in programming mode, and, being formed at predecoding level, involves no integration problems.
摘要翻译：行解码器包括提供有行地址并产生预解码信号的预解码级; 以及最终解码阶段，其基于预解码信号驱动阵列中的各行。预解码阶段包括多个预解码电路，其呈现两个并行信号路径：在读取模式中使用的低电压路径，以及在编程模式中使用的高压路径。 CMOS开关将两路径分开，通过编程模式下的电压转换器由高电压驱动，并且在预解码级别形成，不涉及集成问题。

8. 发明授权

US07168016B2 Method and a device for testing electronic memory devices 有权
标题翻译：方法和用于测试电子存储器件的装置
公开(公告)号：US07168016B2
公开(公告)日：2007-01-23
申请号：US09823926
申请日：2001-03-30
申请人： Giovanni Campardo , Stefano Commodaro , Massimiliano Picca , Patrizia Mongelli
发明人： Giovanni Campardo , Stefano Commodaro , Massimiliano Picca , Patrizia Mongelli
IPC分类号： G11C29/00
CPC分类号： G11C29/56
摘要： A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.
摘要翻译：一种方法和控制装置用于测试电子存储器件。该方法包括将测试数据和/或指令加载到与存储器单元和集成存储电路的矩阵阵列相关联的控制逻辑电路部分中。根据本发明，临时使用测试操作控制装置而不是控制逻辑，测试操作控制装置可以拆卸地外部并连接到存储装置。有利地，测试操作控制设备是存储器外部的矩阵单元阵列。

9. 发明授权

US06249172B1 Circuit for discharging a negative potential node to ground, including control of the discharge current 有权
标题翻译：用于将负电位节点放电到地的电路，包括放电电流的控制
公开(公告)号：US06249172B1
公开(公告)日：2001-06-19
申请号：US09275200
申请日：1999-03-24
申请人： Andrea Ghilardelli , Stefano Commodaro , Maurizio Branchetti , Jacopo Mulatti
发明人： Andrea Ghilardelli , Stefano Commodaro , Maurizio Branchetti , Jacopo Mulatti
IPC分类号： H03K1716
CPC分类号： G11C16/30
摘要： Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.
摘要翻译：用于由电源电压提供的接地电路，包括参考电压，负电位节点，适于将负电位节点与参考电压耦合以响应于控制信号的第一电路。提供第二电路，适于在第一电路中确定用于放电负电位节点的受控电流的通过。

10. 发明申请

US20050240387A1 Gate-level netlist reduction for simulating target modules of a design 失效
标题翻译：用于模拟设计的目标模块的门级网表减少
公开(公告)号：US20050240387A1
公开(公告)日：2005-10-27
申请号：US10832226
申请日：2004-04-26
申请人： Maurizio Spadari , Stefano Commodaro
发明人： Maurizio Spadari , Stefano Commodaro
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for analyzing a circuit design in preparation for a simulation. The method generally includes the steps of (A) marking each of a plurality of modules between a target module of the modules and a top module of the modules in a hierarchy of the circuit design as a first type by traversing upward through the hierarchy starting from the target module, (B) marking each of the modules as a second type where a parent module of the modules is marked as the first type by traversing downward through the hierarchy starting from the top module and (C) marking each of the modules as a third type where the parent module is not marked as the keep type by traversing downward through the hierarchy starting from the top module.
摘要翻译：一种用于分析电路设计以准备仿真的方法。该方法通常包括以下步骤：（A）在电路设计的层级中将模块的目标模块和模块的顶部模块之间的多个模块中的每一个标记为第一类型，方法是从目标模块，（B）将每个模块标记为第二类型，其中模块的父模块被标记为第一类型，通过从顶部模块开始向下穿过层次结构，并且（C）将每个模块标记为第三种类型，通过从顶部模块开始向下遍历层次结构，父模块未标记为保持类型。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式