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1. 发明授权

US08809206B2 Patterned dummy wafers loading in batch type CVD 有权
标题翻译：图案化的假晶片以分批式CVD方式装载
公开(公告)号：US08809206B2
公开(公告)日：2014-08-19
申请号：US13022517
申请日：2011-02-07
申请人： Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
发明人： Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
IPC分类号： H01L21/31
CPC分类号： H01L21/02271 , C23C16/045 , C23C16/44 , C23C16/56 , H01L21/02164 , H01L27/11568
摘要： A method for semiconductor device fabrication is provided. The present invention is directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. At least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
摘要翻译：提供了半导体器件制造方法。本发明涉及在膜沉积系统中使用至少一个图案化虚设晶圆以及一个或多个产品晶片，以产生在所有产品晶片上基本均匀的侧壁层厚度变化。至少一个图案化的虚设晶片可以具有高密度图案化的衬底表面，其具有不同于或基本类似于一个或多个产品晶片的形貌的形貌。此外，在间歇式化学气相沉积（CVD）系统中，至少一个图案化的虚设晶片可以放置在CVD系统的气体入口附近。至少一个图案化的虚设晶片可以放置在CVD系统的排气附近。此外，图案化的虚拟晶片可以在随后的成膜工艺中可重复使用。

2. 发明申请

US20120202355A1 PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD 有权
标题翻译：刻板式CVD中加载的图案式加湿器
公开(公告)号：US20120202355A1
公开(公告)日：2012-08-09
申请号：US13022517
申请日：2011-02-07
申请人： Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
发明人： Rinji Sugino , Bradley Marc Davis , Lei Xue , Kenichi Ohtsuka
IPC分类号： H01L21/465 , H01L21/46
CPC分类号： H01L21/02271 , C23C16/045 , C23C16/44 , C23C16/56 , H01L21/02164 , H01L27/11568
摘要： A method for semiconductor device fabrication is provided. Embodiments of the present invention are directed towards using at least one patterned dummy wafer along with one or more product wafers in a film deposition system to create a sidewall layer thickness variation that is substantially uniform across all product wafers. The at least one patterned dummy wafer may have a high density patterned substrate surface with a topography that is different from or substantially similar to a topography of the one or more product wafers. Furthermore, in a batch type Chemical Vapor Deposition (CVD) system, the at least one patterned dummy wafer may be placed near a gas inlet of the CVD system. In another embodiment, at least one patterned dummy wafer may be placed near an exhaust of the CVD system. Additionally, the patterned dummy wafers may be reusable in subsequent film deposition processes.
摘要翻译：提供了半导体器件制造方法。本发明的实施例涉及在膜沉积系统中使用至少一个图案化虚设晶圆以及一个或多个产品晶片，以产生在所有产品晶片上基本均匀的侧壁层厚度变化。至少一个图案化的虚设晶片可以具有高密度图案化的衬底表面，其具有不同于或基本类似于一个或多个产品晶片的形貌的形貌。此外，在间歇式化学气相沉积（CVD）系统中，至少一个图案化的虚设晶片可以放置在CVD系统的气体入口附近。在另一个实施例中，至少一个图案化虚设晶片可以放置在CVD系统的排气附近。此外，图案化的虚拟晶片可以在随后的成膜工艺中可重复使用。

3. 发明授权

US08143661B2 Memory cell system with charge trap 有权
标题翻译：带电荷陷阱的记忆体系统
公开(公告)号：US08143661B2
公开(公告)日：2012-03-27
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
摘要翻译：提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。

4. 发明授权

US08809936B2 Memory cell system with multiple nitride layers 有权
标题翻译：具有多个氮化物层的存储单元系统
公开(公告)号：US08809936B2
公开(公告)日：2014-08-19
申请号：US11461428
申请日：2006-07-31
申请人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
发明人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
摘要翻译：提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层并且在顶部阻挡中间层上形成接触层。

5. 发明申请

US20080083946A1 MEMORY CELL SYSTEM WITH CHARGE TRAP 有权
标题翻译：带有电荷捕获的存储单元系统
公开(公告)号：US20080083946A1
公开(公告)日：2008-04-10
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792 , H01L21/8238
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, and slot plane antenna plasma oxidizing the charge trap layer for forming a second insulator layer.
摘要翻译：提供了一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，以及缝隙平面天线等离子体氧化用于形成第二绝缘体层的电荷陷阱层。

6. 发明申请

US20080023750A1 MEMORY CELL SYSTEM WITH MULTIPLE NITRIDE LAYERS 有权
标题翻译：具有多层氮化物层的存储单元系统
公开(公告)号：US20080023750A1
公开(公告)日：2008-01-31
申请号：US11461428
申请日：2006-07-31
申请人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
发明人： Lei Xue , Rinji Sugino , YouSeok Suh , Hidehiko Shiraiwa , Meng Ding , Shenqing Fang , Joong Jeon
IPC分类号： H01L29/788
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/513
摘要： A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
摘要翻译：提供一种存储单元系统，包括在半导体衬底上形成第一绝缘体层，在第一绝缘体层上形成电荷陷阱层，在电荷陷阱层上形成第二绝缘体层，在第二绝缘体层上形成顶部阻挡中间层并且在顶部阻挡中间层上形成接触层。

7. 发明授权

US08455268B2 Gate replacement with top oxide regrowth for the top oxide improvement 有权
标题翻译：门顶置换，顶部氧化物再生长，用于顶部氧化物改良
公开(公告)号：US08455268B2
公开(公告)日：2013-06-04
申请号：US11848515
申请日：2007-08-31
申请人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
发明人： Chungho Lee , Hiroyuki Kinoshita , Kuo-Tung Chang , Rinji Sugino , Chi Chang , Huaqiang Wu
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L29/7923 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42348 , H01L29/7887
摘要： Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
摘要翻译：提供了替换/重整存储单元的电荷存储元件周围的顶部氧化物的方法和提高存储单元的电荷存储元件周围的顶部氧化物的质量的方法。该方法可以包括从存储器单元去除第一顶部氧化物上的第一多晶硅; 从存储器单元中去除第一顶部氧化物; 以及在所述电荷存储元件周围形成第二顶部氧化物。可以通过氧化电荷存储元件的一部分或通过在电荷存储元件上形成牺牲层并将牺牲层氧化成第二顶部氧化物来形成第二顶部氧化物。

8. 发明申请

US20080142874A1 INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE 审中-公开
标题翻译：具有氧化铟的集成电路系统
公开(公告)号：US20080142874A1
公开(公告)日：2008-06-19
申请号：US11611860
申请日：2006-12-16
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/792 , H01L29/66833
摘要： A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.
摘要翻译：提供一种用于形成集成电路系统的方法，包括：形成衬底; 在衬底上形成堆叠，所述堆叠具有侧壁并由电荷陷阱层和半导体层形成; 以及缝隙平面天线，用于氧化该叠层以形成具有沿该侧壁的保护层的保护罩。

9. 发明申请

US20080135913A1 MEMORY DEVICE PROTECTION LAYER 有权
标题翻译：存储器件保护层
公开(公告)号：US20080135913A1
公开(公告)日：2008-06-12
申请号：US11608032
申请日：2006-12-07
申请人： Rinji Sugino , Timothy Thurgate , Jean Yee-Mei Yang , Michael Brennan
发明人： Rinji Sugino , Timothy Thurgate , Jean Yee-Mei Yang , Michael Brennan
IPC分类号： H01L29/788
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881
摘要： A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.
摘要翻译：存储器件包括形成在衬底上的一组存储器单元，每个存储器单元包括形成在衬底中的源极区域和漏极区域。存储器件还包括形成在源极区域和漏极区域的顶表面上以及在该组存储器单元的侧表面上的保护层。

10. 发明授权

US06884681B1 Method of manufacturing a semiconductor memory with deuterated materials 有权
标题翻译：用氘代材料制造半导体存储器的方法
公开(公告)号：US06884681B1
公开(公告)日：2005-04-26
申请号：US10672093
申请日：2003-09-26
申请人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
发明人： Tazrien Kamal , Arvind Halliyal , Minh Van Ngo , Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Rinji Sugino
IPC分类号： H01L21/336 , H01L21/8246
CPC分类号： H01L27/11568 , H01L29/66833
摘要： A method for manufacturing a MirrorBit® Flash memory includes providing a semiconductor substrate and successively depositing a first insulating layer, a charge-trapping layer, and a second insulating layer. First and second bitlines are implanted and wordlines are formed before completing the memory. Spacers are formed between the wordlines and an inter-layer dielectric layer is formed over the wordlines. One or more of the second insulating layer, wordlines, spacers, and inter-layer dielectric layers are deuterated, replacing hydrogen bonds with deuterium, thus improving data retention and substantially reducing charge loss.
摘要翻译：一种用于制造MirrorBit（闪存）闪存的方法包括：提供半导体衬底，并依次沉积第一绝缘层，电荷俘获层和第二绝缘层。植入第一和第二位线，并在完成内存之前形成字线。在字线之间形成间隔，并且在字线之间形成层间电介质层。第二绝缘层，字线，间隔层和层间电介质层中的一个或多个被氘化，用氘替代氢键，从而改善数据保留并显着降低电荷损失。

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