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1. 发明授权

US4984203A High speed static BiCMOS memory with dual read ports 失效
标题翻译：具有双重读取端口的高速静态BiCMOS存储器
公开(公告)号：US4984203A
公开(公告)日：1991-01-08
申请号：US453567
申请日：1989-12-20
申请人： Rimon Shookhtim , Lo-Shan Lee , Babak Mansoorian
发明人： Rimon Shookhtim , Lo-Shan Lee , Babak Mansoorian
IPC分类号： G11C8/16
CPC分类号： G11C8/16
摘要： A memory includes a plurality of cells with each cell containing a pair of cross-coupled N-channel field-effect transistors having set a reset nodes. Also in each cell, a first P-channel transistor couples a first select line to the set node; a first bipolar transistor couples the set node to a first bit line; a second P-channel trnasistor couples a second select line to the reset node; and a second bipolar transistor couples the reset node to a second bit line. Data is read from one port of the cell by pulling up just the set node via the first selected line and first P-channel transistor; and data is read from another port of the cell by pulling up just the reset node via the second select line and second P-channel transistor. Both such reads are fast since the parasitic capacitance of each select line is dependent on just a single pull-up transistor per cell. Also the cell is small in size since it is made with two less transistors than a conventional cell.
摘要翻译：存储器包括多个单元，每个单元包含设置复位节点的一对交叉耦合N沟道场效应晶体管。此外，在每个单元中，第一P沟道晶体管将第一选择线耦合到集合节点; 第一双极晶体管将集合节点耦合到第一位线; 第二P沟道三通管将第二选择线耦合到复位节点; 并且第二双极晶体管将复位节点耦合到第二位线。通过经由第一选择线和第一P沟道晶体管仅提取集合节点从单元的一个端口读取数据; 并且通过经由第二选择线和第二P沟道晶体管仅提取复位节点而从单元的另一个端口读取数据。这两种读取都是快速的，因为每个选择线的寄生电容仅取决于每个单元的单个上拉晶体管。此外，电池的尺寸小，因为其由比现有电池少两个晶体管制成。

2. 发明授权

US5047980A BiCMOS memory having memory cells connected directly to address decoders 失效
标题翻译：具有直接连接到地址解码器的存储单元的BiCMOS存储器
公开(公告)号：US5047980A
公开(公告)日：1991-09-10
申请号：US569673
申请日：1990-08-17
申请人： Rimon Shookhtim , Lo-Shan Lee , Babak Mansoorian
发明人： Rimon Shookhtim , Lo-Shan Lee , Babak Mansoorian
IPC分类号： G11C11/415 , G11C8/08 , G11C8/10 , G11C11/413
CPC分类号： G11C8/10 , G11C8/08
摘要： A digital BiCMOS memory chip includes a row of memory cells, and an addressing circuit for the row of cells. Each of the memory cells is constructed of field-effect transistors which operate at CMOS voltage levels, whereas the address decorder is constructed of bipolar transistors which operate at ECL voltage levels. A direct connection is made via a row line from the address decoder to the row of memory cells with no ECL-to-CMOS voltage level converter lying there between. This direct connection is made operable by properly selecting all voltages that occur on certain nodes in the address decoder and the memory cell. And, it enables the memory to be read faster plus occupy less chip space and dissipate less power than the prior art.
摘要翻译：数字BiCMOS存储器芯片包括一行存储器单元，以及用于该行单元的寻址电路。每个存储单元由以CMOS电压电平工作的场效应晶体管构成，而地址解码由以ECL电压电平工作的双极晶体管构成。通过从地址解码器到存储单元行的行线进行直接连接，其间没有ECL至CMOS电压电平转换器。通过适当地选择在地址解码器和存储单元中的某些节点上发生的所有电压，可以实现该直接连接。并且，它使得能够更快地读取存储器，同时占用更少的芯片空间并且消耗比现有技术更少的功率。

3. 发明授权

US06725443B1 Integrated circuit template cell system and method 有权
标题翻译：集成电路模板单元系统及方法
公开(公告)号：US06725443B1
公开(公告)日：2004-04-20
申请号：US10280978
申请日：2002-10-24
申请人： Simon S. Pang , Rimon Shookhtim , Joseph J. Balardeta , Gary Wong
发明人： Simon S. Pang , Rimon Shookhtim , Joseph J. Balardeta , Gary Wong
IPC分类号： G06F1750
CPC分类号： H01L27/0292 , G06F17/5077 , H01L23/50 , H01L27/0251 , H01L27/11898 , H01L2924/0002 , H01L2924/00
摘要： A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.
摘要翻译：提供了一种用于在集成电路（IC）的输入/输出（I / O）表面上形成模板单元的系统和方法。电池的第一金属层包括从电池的一个边缘延伸到另一边缘的多条平行的总线。第二底层金属层包括沿与第一层线垂直的方向延伸的总线线。信号路由层位于第二金属层下面，路由通道位于单元的边缘周围，并且ESD和输出缓冲电路放置在路由通道内。第一和第二金属层的总线以及信号路由层的路由信道具有连接区域，从而通过邻接单元形成连接。每个单元还包括覆盖在第一金属层上的倒装芯片焊盘，该焊盘可以通过通孔连接到第一或第二金属层。

4. 发明授权

US06570916B1 Adaptive equalization circuit and method 失效
标题翻译：自适应均衡电路及方法
公开(公告)号：US06570916B1
公开(公告)日：2003-05-27
申请号：US08811414
申请日：1997-03-04
申请人： David W. Feldbaumer , Mark B. Weaver , Rimon Shookhtim , Cecil Aswell
发明人： David W. Feldbaumer , Mark B. Weaver , Rimon Shookhtim , Cecil Aswell
IPC分类号： H03H740
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/0812 , H04L7/0331 , H04L25/03885
摘要： A timing based adaptive equalization circuit (10) dynamically monitors a signal received at an input terminal (16) and compensates for attenuation losses in the transmission of the signal by adjusting an equalization value that increases or decreases the equalization of the signal. A digital phase locked loop control circuit (26) centers the transition of the equalized signal in a delay line circuit (31). An analog delay locked loop circuit (29) provides a fixed throughput time for matching delay elements of delay line circuits (31, 41 and 51) in the adaptive equalization circuit (10). Timing signals propagating in the delay line circuits (31, 41 and 51) are stored in sampler circuits (36, 46 and 56). The equalization value for equalizing the input signal is adjusted based on stored logic values of specific storage elements in the sampler circuits (46 and 56).
摘要翻译：基于定时的自适应均衡电路（10）动态地监视在输入端（16）处接收到的信号，并通过调整增加或减少信号均衡的均衡值来补偿信号传输中的衰减损耗。数字锁相环控制电路（26）使均衡信号在延迟线电路（31）中的转变居中。模拟延迟锁定环电路（29）为自适应均衡电路（10）中的延迟线路电路（31,41和51）的延迟元件的匹配提供固定的吞吐时间。在延迟线电路（31,41和51）中传播的定时信号被存储在采样器电路（36,46和56）中。基于采样器电路（46和56）中的特定存储元件的存储逻辑值来调整用于均衡输入信号的均衡值。

5. 发明授权

US06502231B1 Integrated circuit template cell system and method 有权
标题翻译：集成电路模板单元系统及方法
公开(公告)号：US06502231B1
公开(公告)日：2002-12-31
申请号：US09871473
申请日：2001-05-31
申请人： Simon S. Pang , Rimon Shookhtim , Joseph J. Balardeta , Gary Wong
发明人： Simon S. Pang , Rimon Shookhtim , Joseph J. Balardeta , Gary Wong
IPC分类号： G06F1750
CPC分类号： H01L27/0292 , G06F17/5077 , H01L23/50 , H01L27/0251 , H01L27/11898 , H01L2924/0002 , H01L2924/00
摘要： A system and method are provided for forming a template cell on the input/output (I/O) surface of an integrated circuit (IC). The first metal layer of the cell includes a plurality of parallel bus lines extending from one edge of the cell to the other. A second underlying metal layer includes bus lines extending in an orthogonal direction to the first layer lines. A signal routing layer underlies the second metal layer, with a routing channel located around the edges of the cell, and ESD and output buffer circuits placed inside of the routing channel. The bus lines of the first and second metal layers, and the routing channel of the signal routing layer, have connection areas so that connections are formed by abutting the cells. Each cell also includes a flip-chip solder pad overlying the first metal layer that can be connected by a via to either the first or second metal layer.
摘要翻译：提供了一种用于在集成电路（IC）的输入/输出（I / O）表面上形成模板单元的系统和方法。电池的第一金属层包括从电池的一个边缘延伸到另一边缘的多条平行的总线。第二底层金属层包括沿与第一层线垂直的方向延伸的总线线。信号路由层位于第二金属层下面，路由通道位于单元的边缘周围，并且ESD和输出缓冲电路放置在路由通道内。第一和第二金属层的总线以及信号路由层的路由信道具有连接区域，从而通过邻接单元形成连接。每个单元还包括覆盖在第一金属层上的倒装芯片焊盘，该焊盘可以通过通孔连接到第一或第二金属层。

6. 发明授权

US5586046A Computer implemented method for generating an integrated circuit design 失效
标题翻译：用于生成集成电路设计的计算机实现方法
公开(公告)号：US5586046A
公开(公告)日：1996-12-17
申请号：US330463
申请日：1994-10-28
申请人： David Feldbaumer , Frederick L. Lum , Vickie Mercier , Mark B. Weaver , Jan-Chung Wong , Rimon Shookhtim
发明人： David Feldbaumer , Frederick L. Lum , Vickie Mercier , Mark B. Weaver , Jan-Chung Wong , Rimon Shookhtim
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A computer implemented method for generating an integrated circuit design (11) is provided. A description of a circuit (16) is provided in a format such as a Hardware Description Language (12). A functional simulation (17) of the description is run to determine functionality of the circuit. A netlist conversion (18) converts the description to a netlist comprising both a single-ended and differential circuit. The netlist conversion (18) converts the description to a single-ended description (24), replaces single-ended cells with differential cells and interconnects the differential cells (25), and exchanges terminals of the differential cells to maintain logic equivalence (26). A simulation with timing (19) is run on the netlist to verify timing characteristics of the circuit. The netlist is then provided to a router to generate a physical circuit layout (20) having both single-ended and differential circuits.
摘要翻译：提供了一种用于生成集成电路设计（11）的计算机实现方法。以诸如硬件描述语言（12）的格式提供电路（16）的描述。执行描述的功能模拟（17）以确定电路的功能。网表转换（18）将描述转换成包括单端和差分电路的网表。网表转换（18）将描述转换为单端描述（24），用差分单元替换单端单元并互连差分单元（25），并交换差分单元的端子以保持逻辑等效性（26）。在网表上运行具有定时（19）的仿真，以验证电路的定时特性。然后将网表提供给路由器以产生具有单端和差分电路的物理电路布局（20）。

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