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1. 发明申请

US20060124927A1 FORMING OF HIGH ASPECT RATIO CONDUCTIVE STRUCTURE USING INJECTION MOLDED SOLDER 有权
标题翻译：高比例导电结构的形成
公开(公告)号：US20060124927A1
公开(公告)日：2006-06-15
申请号：US10905013
申请日：2004-12-09
申请人： Robert Groves , Peter Gruber , Kevin Petrarca , Richard Volant , George Walker
发明人： Robert Groves , Peter Gruber , Kevin Petrarca , Richard Volant , George Walker
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H05K3/3468 , G01R1/07314 , G01R3/00 , H01L21/4853 , H01L21/6835 , H01L24/11 , H01L2224/13099 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/01013 , H01L2924/01018 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01058 , H01L2924/01066 , H01L2924/01067 , H01L2924/01068 , H01L2924/01075 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/19041 , H01L2924/19042 , H05K3/325 , H05K2201/09745 , H05K2201/10734 , H05K2203/0113 , H05K2203/0338 , H05K2203/128 , H05K2203/162 , H05K2203/167 , H01L2224/0401
摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.
摘要翻译：公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。导电结构包括通过注射成型的焊料形成的高纵横比结构。本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。此外，该方法可以向后兼容并可定制。

2. 发明申请

US20070059951A1 Flexible assembly of stacked chips 有权
标题翻译：堆叠芯片的灵活组装
公开(公告)号：US20070059951A1
公开(公告)日：2007-03-15
申请号：US10573561
申请日：2003-09-30
申请人： Richard Volant , Kevin Petrarca , George Walker
发明人： Richard Volant , Kevin Petrarca , George Walker
IPC分类号： H05K1/00
CPC分类号： H01L25/0657 , H01L21/568 , H01L21/6835 , H01L23/5387 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/50 , H01L2221/68359 , H01L2221/68372 , H01L2224/04042 , H01L2224/04105 , H01L2224/05554 , H01L2224/18 , H01L2224/24137 , H01L2224/48091 , H01L2224/48227 , H01L2224/49431 , H01L2224/49433 , H01L2224/73209 , H01L2224/73259 , H01L2224/73267 , H01L2224/82005 , H01L2224/9222 , H01L2225/06524 , H01L2225/06527 , H01L2225/06579 , H01L2225/06589 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A three-dimensional package consisting of a plurality of folded integrated circuit chips (100, 110, 120) is described wherein at least one chip provides interconnect pathways for electrical connection to additional chips of the stack, and at least one chip (130) is provided with additional interconnect wiring to a substrate (500), package or printed circuit board. Further described, is a method of providing a flexible arrangement of interconnected chips that are folded over into a three-dimensional arrangements to consume less aerial space when mounted on a substrate, second-level package or printed circuit board.
摘要翻译：描述了由多个折叠集成电路芯片（100,110,120）组成的三维封装，其中至少一个芯片提供用于与堆叠的附加芯片的电连接的互连路径，并且至少一个芯片（130）是提供与衬底（500），封装或印刷电路板的附加互连布线。进一步描述的是提供互连芯片的柔性布置的方法，其被折叠成三维布置以在安装在基板，二级封装或印刷电路板上时消耗较少的空中空间。

3. 发明申请

US20080106872A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
标题翻译：高密度集成电路设备，测试探针及其使用方法
公开(公告)号：US20080106872A1
公开(公告)日：2008-05-08
申请号：US11930045
申请日：2007-10-30
申请人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
发明人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
IPC分类号： H05K1/14
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.
摘要翻译：本发明涉及一种高密度测试探针，其提供用于测试晶片形式的高密度和高性能集成电路或作为离散芯片的装置。测试探针由嵌入柔性或高模量弹性体材料的细长电导体的密集阵列形成。陶瓷集成电路芯片封装基板等标准封装基板用于提供空间变压器引线与空间变压器表面的接触焊盘阵列接合。空间变压器由多层集成电路芯片封装基板形成。电线与接触位置阵列一样密集。围绕着向外突出的线的阵列设置模具。液体弹性体设置在模具中以填充电线之间的空间。弹性体被固化并且模具被去除，留下布置在弹性体中并且与空间变压器电接触的线阵列。空间变压器可以具有一组引脚，这些引脚位于空间变压器的相反表面上，其中细长导体被接合。这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。或者，插入器电连接器可以设置在第一和第二空间变压器之间。

4. 发明申请

US20080106291A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
标题翻译：高密度集成电路设备，测试探针及其使用方法
公开(公告)号：US20080106291A1
公开(公告)日：2008-05-08
申请号：US11930638
申请日：2007-10-31
申请人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
发明人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
IPC分类号： G01R31/02
CPC分类号： G01R1/07371 , G01R1/06711 , G01R1/0675 , G01R1/07307 , G01R1/07314 , G01R1/07342 , G01R1/07378 , G01R3/00 , G01R31/2886 , H01L23/49827 , H01L23/5384 , H01L24/45 , H01L24/48 , H01L25/0652 , H01L2224/1134 , H01L2224/13099 , H01L2224/16 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45155 , H01L2224/45164 , H01L2224/48091 , H01L2224/48227 , H01L2224/78301 , H01L2224/85205 , H01L2224/85214 , H01L2924/00013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/1627 , H01L2924/181 , H01L2924/19107 , H01L2924/3011 , Y10S29/029 , Y10T29/49004 , Y10T29/49126 , Y10T29/49147 , Y10T29/49149 , Y10T29/49158 , Y10T29/49162 , Y10T29/49192 , Y10T29/53174 , H01L2924/00 , H01L2924/00014 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer forms or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer. The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.
摘要翻译：本发明涉及一种高密度测试探针，其提供用于测试晶片形式的高密度和高性能集成电路或作为分立芯片的装置。测试探针由嵌入柔性或高模量弹性体材料的细长电导体的密集阵列形成。使用陶瓷集成电路芯片封装基板等标准封装基板来提供空间变压器。电线被连接到空间变压器表面上的接触焊盘阵列。空间变压器由多层集成电路芯片封装基板形成。电线与接触位置阵列一样密集。围绕着向外突出的线的阵列设置模具。液体弹性体设置在模具中以填充电线之间的空间。弹性体被固化并且模具被去除，留下布置在弹性体中并与空间变压器电接触的线阵列。空间变压器可以具有一个引脚阵列，它们在空间变压器的与细长导体所接合的相反的表面上。这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。或者，插入器电连接器可以设置在第一和第二空间变压器之间。

5. 发明申请

US20070166777A1 Methods for detecting lp-pla2 activity and inhibition of lp-pla2 activity 审中-公开
标题翻译：检测lp-pla2活性和抑制lp-pla2活性的方法
公开(公告)号：US20070166777A1
公开(公告)日：2007-07-19
申请号：US10599914
申请日：2005-04-14
申请人： Yaping Shou , Yin-Fai Siu , George Walker
发明人： Yaping Shou , Yin-Fai Siu , George Walker
IPC分类号： C12Q1/48 , C12Q1/34
CPC分类号： C12Q1/61 , C12Q1/34 , C12Q1/44 , C12Q2334/10 , G01N2333/918
摘要： This invention relates to methods for determining the activity of Lp-PLA2 in at least one sample from an animal. The invention also relates to methods for determining the inhibition of Lp-PLA2 activity in samples from animals that are administered an Lp-PLA2 inhibitor.
摘要翻译：本发明涉及用于测定来自动物的至少一种样品中Lp-PLA2的活性的方法。本发明还涉及用于测定来自施用Lp-PLA2抑制剂的动物的样品中Lp-PLA2活性的抑制的方法。

6. 发明申请

US20060110754A1 Amplification and separation of nucleic acid sequences using strand displacement amplification and bioelectronic microchip technology 审中-公开
公开(公告)号：US20060110754A1
公开(公告)日：2006-05-25
申请号：US11251229
申请日：2005-10-14
申请人： Michael Nerenberg , Carl Edman , Catherine Spargo , George Walker
发明人： Michael Nerenberg , Carl Edman , Catherine Spargo , George Walker
IPC分类号： C12Q1/68 , C12P19/34 , C12M1/34
CPC分类号： C12Q1/6844 , C12P19/34 , C12Q1/6825 , C12Q1/6837 , C12Q2537/143 , C12Q2531/119 , C12Q2565/501 , C12Q2565/607
摘要： Described and disclosed are devices, methods, and compositions of matter for the multiplex amplification and analysis of nucleic acid sequences in a sample using novel strand displacement amplification technologies in combination with bioelectronic microchip technology. Specifically, a nucleic acid in a sample is amplified to form amplicons, the amplicons are addressed to specified electronically addressable capture sites of the bioelectronic microchip, the addressed amplicons are captured and labeled, and then the capture sites are analyzed for the presence of label. Samples may be amplified using strand displacement amplification. The invention is also amenable to other amplification methodologies well known by those skilled in the art. The capture and label steps may be by a method of universal capture with sequence specific reporter, or by a method of sequence specific capture with universal reporter. The label may be detected by fluorescence, chemiluminescence, elecrochemiluminescence, or any other technique as are well known by those skilled in the art. This invention further allows for analyzing multiple nucleic acid targets on a single diagnostic platform wherein the nucleic acids may be amplified while either in direct contact with microchip components or in solution above the microchip array.

7. 发明申请

US20060027934A1 Silicon chip carrier with conductive through-vias and method for fabricating same 审中-公开
标题翻译：具有导电通孔的硅芯片载体及其制造方法
公开(公告)号：US20060027934A1
公开(公告)日：2006-02-09
申请号：US11242221
申请日：2005-10-03
申请人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker , Yu-Ting Cheng , Kenneth Ocheltree , Robert Montoye
发明人： Daniel Edelstein , Paul Andry , Leena Buchwalter , Jon Casey , Sherif Goma , Raymond Horton , Gareth Hougham , Michael Lane , Xiao Liu , Chirag Patel , Edmund Sprogis , Michelle Steen , Brian Sundlof , Cornelia Tsang , George Walker , Yu-Ting Cheng , Kenneth Ocheltree , Robert Montoye
IPC分类号： H01L23/48
CPC分类号： H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
摘要翻译：一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于或者与衬底的密切匹配。导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯，具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

8. 发明申请

US20050062492A1 High density integrated circuit apparatus, test probe and methods of use thereof 审中-公开
标题翻译：高密度集成电路设备，测试探针及其使用方法
公开(公告)号：US20050062492A1
公开(公告)日：2005-03-24
申请号：US10408200
申请日：2003-04-04
申请人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
发明人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
IPC分类号： G01R1/067 , G01R1/073 , G01R3/00 , H05K1/00 , G01R31/02 , G01R31/26
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.
摘要翻译：本发明涉及一种高密度测试探针，其提供用于测试晶片形式的高密度和高性能集成电路或作为离散芯片的装置。测试探针由嵌入柔性或高模量弹性体材料的细长电导体的密集阵列形成。使用陶瓷集成电路芯片封装基板等标准封装基板来提供空间变压器。电线被连接到空间变压器表面上的接触焊盘阵列。空间变压器由多层集成电路芯片封装基板形成。电线与接触位置阵列一样密集。围绕着向外突出的线的阵列设置模具。液体弹性体设置在模具中以填充电线之间的空间。弹性体被固化并且模具被去除，留下布置在弹性体中并且与空间变压器电接触的线阵列。空间变压器可以具有一组引脚，这些引脚位于空间变压器的相反表面上，其中细长导体被接合。这些销插入第二空间变压器（例如印刷电路板）上的插座中以形成探针组件。或者，插入器电连接器可以设置在第一和第二空间变压器之间。

9. 发明授权

US4367148A Method of and apparatus for separating liquid from solids entrained therein 失效
标题翻译：从夹带的固体中分离液体的方法和设备
公开(公告)号：US4367148A
公开(公告)日：1983-01-04
申请号：US247139
申请日：1981-03-24
申请人： Robert Fulton , George Walker
发明人： Robert Fulton , George Walker
IPC分类号： B01D21/24 , B05B15/12 , C02F1/24
CPC分类号： B01D21/2433 , B05B15/1266 , Y10S55/46
摘要： The invention relates to a method of and apparatus for separating liquid from solids entrained therein, which solids, preferably paint particles emanating from a paint spray booth are capable of floating on the liquid. The liquid and solids are entrained in a collector which is open to atmosphere and in which a Coanda - type flow prevails so that the solids are collected as a skin on the surface of the liquid. In one embodiment the level of the liquid is raised so that the skin slips over a lip and out of the collector, leaving the liquid behind; in another embodiment the skin is collected behind a restraining device which is moved to allow the skin to flow through an outlet therefor, again leaving the liquid behind.
摘要翻译：本发明涉及一种从携带在其中的固体分离液体的方法和装置，该固体，优选从喷漆室排出的涂料颗粒能够漂浮在液体上。液体和固体被夹带在对大气开放的收集器中，其中以柯安达型流动流动，使得固体作为皮肤收集在液体的表面上。在一个实施例中，液体的水平升高，使得皮肤滑过唇缘并离开收集器，留下液体; 在另一个实施方案中，皮肤被收集在限制装置的后面，该限制装置被移动以允许皮肤流过其出口，再次将液体留在后面。

10. 发明申请

US20080106281A1 HIGH DENSITY INTEGRATED CIRCUIT APPARATUS, TEST PROBE AND METHODS OF USE THEREOF 审中-公开
公开(公告)号：US20080106281A1
公开(公告)日：2008-05-08
申请号：US11929754
申请日：2007-10-30
申请人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
发明人： Brian Beaman , Keith Fogel , Paul Lauro , Maurice Norcott , Da-Yuan Shih , George Walker
IPC分类号： G01R31/26
CPC分类号： G01R1/0735 , G01R1/06744 , G01R1/0675 , G01R1/07307 , G01R1/07378 , G01R3/00
摘要： The present invention is directed to a high density test probe which provides a means for testing a high density and high performance integrated circuits in wafer form or as discrete chips. The test probe is formed from a dense array of elongated electrical conductors which are embedded in an compliant or high modulus elastomeric material. A standard packaging substrate, such as a ceramic integrated circuit chip packaging substrate is used to provide a space transformer. Wires are bonded to an array of contact pads on the surface of the space transformer. The space transformer formed from a multilayer integrated circuit chip packaging substrate. The wires are as dense as the contact location array. A mold is disposed surrounding the array of outwardly projecting wires. A liquid elastomer is disposed in the mold to fill the spaces between the wires. The elastomer is cured and the mold is removed, leaving an array of wires disposed in the elastomer and in electrical contact with the space transformer The space transformer can have an array of pins which are on the opposite surface of the space transformer opposite to that on which the elongated conductors are bonded. The pins are inserted into a socket on a second space transformer, such as a printed circuit board to form a probe assembly. Alternatively, an interposer electrical connector can be disposed between the first and second space transformer.

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