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    • 1. 发明授权
    • Stack memory selection upon exception in a data processing system
    • 在数据处理系统中的异常堆栈存储器选择
    • US07797681B2
    • 2010-09-14
    • US11431926
    • 2006-05-11
    • Richard Roy GrisenthwaitePaul KimelmanDavid James SealDavid Aaron Rusling
    • Richard Roy GrisenthwaitePaul KimelmanDavid James SealDavid Aaron Rusling
    • G06F9/44
    • G06F9/4812G06F9/3861G06F9/462
    • A data processor 2 has privilege levels associated with it including a user level and a privileged level. The processor 2 also has multiple stack memories which can be used including one or more process stacks, a main stack and a deep stack. The stack memory to be used is de-coupled from the privilege level. An activation level state variable tracking the number of pending exceptions is held by the processor and used to modify which stack memory stores pending state values when an exception occurs. If the system is at a base level of activation, corresponding to currently no pending exceptions, then when an exception occurs the current state data is saved on the process stack with the main stack being available for the exception handling code. Particular exceptions can be flagged as requiring use of a deep stack rather than either the process stack or the main stack. If the system is not at the base level of activation, then the main stack is used to save state variables when an exception occurs rather than the process stack.
    • 数据处理器2具有与其相关联的特权级别,其包括用户级别和特权级别。 处理器2还具有可以使用的多个堆栈存储器,包括一个或多个处理堆栈,主堆栈和深堆栈。 要使用的堆栈内存从特权级别去耦合。 跟踪待处理异常的数量的激活级状态变量由处理器保存,并用于修改哪个堆栈存储器在发生异常时存储待处理的状态值。 如果系统处于激活的基本级别,对应于当前没有挂起的异常,则当发生异常时,当前状态数据保存在进程堆栈中,主堆栈可用于异常处理代码。 可以将特殊异常标记为需要使用深栈,而不是使用进程堆栈或主堆栈。 如果系统不在激活的基本级别,则主堆栈用于在异常发生时保存状态变量而不是进程堆栈。
    • 2. 发明授权
    • Data processing apparatus having memory protection unit
    • 具有存储器保护单元的数据处理装置
    • US07068545B1
    • 2006-06-27
    • US11028501
    • 2005-01-04
    • Paul KimelmanRichard Roy GrisenthwaiteDavid James Seal
    • Paul KimelmanRichard Roy GrisenthwaiteDavid James Seal
    • G11C7/00
    • G06F12/1441
    • A data processor (100) has a memory operable to store data values; a memory protection unit (130) operable to associate memory attributes with portions of said memory and to identify a plurality of memory regions corresponding to respective address ranges of said memory. The memory protection unit is operable to associate with at least one of the plurality of memory regions (150) a respective memory region specifier comprising an attributes field (230) for defining a set of memory attributes associated with said memory region and a sub-region field (240) for holding a sub-region membership value. The sub-region membership value specifies, for each of a plurality of sub-regions of the memory region, whether respective sub-regions (160-1 to 160-8) are member sub-regions or non-member sub-regions such that said memory attributes are applied to said member sub-regions but are not applied to said non-member sub-regions.
    • 数据处理器(100)具有可操作以存储数据值的存储器; 存储器保护单元(130),其可操作以将存储器属性与所述存储器的部分相关联,并且识别对应于所述存储器的相应地址范围的多个存储器区域。 存储器保护单元可操作以将多个存储器区域(150)中的至少一个与相应的存储器区域说明符相关联,该存储器区域说明符包括用于定义与所述存储器区域相关联的一组存储器属性的属性字段(230)和子区域 用于保存子区域成员值的字段(240)。 子区域成员关系值针对存储区域的多个子区域中的每一个指定各个子区域(160-1至160-8)是否是成员子区域或非成员子区域,使得 所述存储器属性被应用于所述成员子区域,但不应用于所述非成员子区域。
    • 4. 发明授权
    • Performing diagnostic operations upon a data processing apparatus with power down support
    • 对具有断电支持的数据处理设备执行诊断操作
    • US07228457B2
    • 2007-06-05
    • US10801131
    • 2004-03-16
    • Conrado Blasco AlluePaul KimelmanAndrew Brookfield SwaineRichard Roy Grisenthwaite
    • Conrado Blasco AlluePaul KimelmanAndrew Brookfield SwaineRichard Roy Grisenthwaite
    • G06F11/00
    • G06F11/2236
    • A system-on-chip integrated circuit 2 is provided with multiple data processing circuits 4, 6, 8 each with an associated diagnostic interface circuit 16, 18, 20 connected via a diagnostic transaction bus 14 to a diagnostic transaction master circuit 12. The diagnostic master transaction circuit 12 issues diagnostic transaction requests to the diagnostic interface circuits 16, 18, 20. If the associated data processing circuits 4, 6, 8 are powered-down, or otherwise non responsive, then the diagnostic interface circuit 16, 18, 20 returns a diagnostic bus transaction error signal to the diagnostic transaction master circuit 12. A sticky-bit latch 30 within each diagnostic interface circuit 16, 18, 20 serves to record a power-down event and force generation of the diagnostic bus transaction error signal until that sticky bit is cleared by the diagnostic mechanisms. This ensure the diagnostic mechanisms are made aware of the power-down event so they may take any appropriate remedial action that might be necessary as a result of that power-down event.
    • 系统级芯片集成电路2具有多个数据处理电路4,6,8,每个数据处理电路具有通过诊断事务总线14连接到诊断事务主电路12的相关联的诊断接口电路16,18,20。 诊断主交易电路12向诊断接口电路16,18,20发出诊断事务请求。 如果相关联的数据处理电路4,6,8被断电或以其他方式不响应,则诊断接口电路16,18,20将诊断总线事务错误信号返回给诊断事务主电路12。 每个诊断接口电路16,18,20内的粘滞锁存器30用于记录诊断总线事务错误信号的掉电事件和强制产生,直到诊断机构清除该粘滞位。 这样可以确保诊断机制能够意识到掉电事件,因此可能会由于断电事件而采取任何必要的补救措施。
    • 5. 发明授权
    • Management of polling loops in a data processing apparatus
    • 管理数据处理设备中的轮询循环
    • US07805550B2
    • 2010-09-28
    • US11032226
    • 2005-01-11
    • Paul KimelmanRichard Roy Grisenthwaite
    • Paul KimelmanRichard Roy Grisenthwaite
    • G06F3/00G06F15/16G06F15/00
    • G06F13/24G06F1/3228
    • A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode. This provides a particularly efficient technique for managing a polling loop within the data processing apparatus.
    • 提供了一种用于管理轮询循环的数据处理装置和方法。 数据处理装置包括主处理单元和辅助处理单元,可操作以代表主处理单元执行任务。 辅助处理单元可操作以在任务完成时设置完成字段,并且主处理单元可操作地轮询完成字段以便确定任务是否已经完成。 如果在轮询完成字段时,主处理单元确定任务尚未完成的阈值次数,则主处理单元可操作以进入省电模式。 当完成任务时,辅助处理单元可操作地在连接主处理单元和辅助处理单元的路径上发出通知。 主处理单元在接收到退出省电模式的通知时被布置。 这提供了一种用于管理数据处理装置内的轮询循环的特别有效的技术。
    • 6. 发明授权
    • Forced diagnostic entry upon power-up
    • 上电时强制诊断输入
    • US07426659B2
    • 2008-09-16
    • US11085263
    • 2005-03-22
    • Conrado Blasco AlluePaul KimelmanAndrew Brookfield SwaineRichard Roy Grisenthwaite
    • Conrado Blasco AlluePaul KimelmanAndrew Brookfield SwaineRichard Roy Grisenthwaite
    • G06F11/00
    • G06F11/079G06F11/2733
    • A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.
    • 描述了具有中央处理单元4和诊断机构10的数据处理系统2.中央处理单元4可切换到能够恢复到正常操作模式的掉电模式。 当中央处理单元4恢复到正常操作模式时,诊断机构10禁止程序指令的执行,以允许对诊断机构进行适当的编程,使得立即上电代码和操作能被正确诊断。 通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。 程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。
    • 9. 发明申请
    • Microcontroller with Embedded Secure Feature
    • 具有嵌入式安全功能的微控制器
    • US20120265975A1
    • 2012-10-18
    • US13439530
    • 2012-04-04
    • Paul Kimelman
    • Paul Kimelman
    • G06F21/00G06F9/44
    • G06F21/57G06F9/44505G06F21/53G06F21/76G06F2221/2105
    • A secure environment is established within a system on a chip (SoC) without the use of a memory management unit. A set of security parameters is produced by a configuration program executed by a processor within the SoC that is read from a first non-volatile memory within the SoC. A set of stored parameters is created in a committable non-volatile memory within the SoC by writing the set of security parameters into the committable non-volatile memory. The committable non-volatile memory is sealed so that that it cannot be read or written by the processor after being sealed. The stored parameters can then be accessed only by control circuitry. Security circuitry within the SoC is configured using the stored parameters each time the SoC is initialized and thereby enforces the secure environment within the SoC.
    • 在芯片(SoC)系统内建立安全环境,而不使用内存管理单元。 由SoC内的处理器执行的配置程序产生一组安全参数,该处理器从SoC中的第一非易失性存储器读取。 通过将一组安全参数写入到可提交的非易失性存储器中,在SoC中的提交的非易失性存储器中创建一组存储的参数。 可提交的非易失性存储器被密封,使得在密封之后它不能被处理器读取或写入。 所存储的参数只能由控制电路访问。 每次SoC初始化时,使用存储的参数来配置SoC内的安全电路,从而实现SoC内的安全环境。