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1. 发明授权

US06418505B1 Accessing beyond memory address range of commodity operating system using enhanced operating system adjunct processor interfaced to appear as RAM disk 有权
标题翻译：使用增强型操作系统辅助处理器访问超出内存地址范围的商品操作系统，显示为RAM磁盘
公开(公告)号：US06418505B1
公开(公告)日：2002-07-09
申请号：US09215629
申请日：1998-12-17
申请人： Richard R. Barton , Peter Washington , John H. Waters
发明人： Richard R. Barton , Peter Washington , John H. Waters
IPC分类号： G06F1200
CPC分类号： G06F3/0613 , G06F3/064 , G06F3/0679 , G06F12/0292 , G06F12/0623
摘要： A multi-processor computer system that includes at least one “regular” processor and one “enhanced mode” processor. The enhanced mode processor is preferably not turned over to the regular processor, but is initialized to look like an internal or external device, such as a disk drive or the like. In a preferred embodiment, fast access memory that is outside the addressable range of the regular processor is coupled to the enhanced mode processor and accessed through a RAM-disk device driver. In this manner, the amount of fast access memory available to the regular processor is increased.
摘要翻译：包括至少一个“常规”处理器和一个“增强模式”处理器的多处理器计算机系统。增强型处理器优选地不转换到常规处理器，而是被初始化为看起来像内部或外部设备，例如磁盘驱动器等。在优选实施例中，在常规处理器的可寻址范围之外的快速存取存储器耦合到增强模式处理器并通过RAM盘驱动器访问。以这种方式，普通处理器可用的快速存取存储器的数量增加。

2. 发明授权

US5860141A Method and apparatus for enabling physical memory larger than corresponding virtual memory 失效
标题翻译：用于使物理存储器大于相应的虚拟存储器的方法和装置
公开(公告)号：US5860141A
公开(公告)日：1999-01-12
申请号：US763918
申请日：1996-12-11
申请人： Peter Washington , John H. Waters , Richard R. Barton , Vernon K. Boland
发明人： Peter Washington , John H. Waters , Richard R. Barton , Vernon K. Boland
IPC分类号： G06F12/02 , G06F12/06 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0292 , G06F12/109 , G06F12/0623
摘要： A method and apparatus for enabling a physical memory larger than a corresponding virtual memory. An apparatus is disclosed that includes a processor having an address word of a predefined length, a main memory having a size larger than the addressable range of the predefined address word, and virtual memory logic for configuring the processor virtual memory to contain a subset of the main memory as resident memory and pointers to the remainder of main memory. Analogous method steps are disclosed as is dividing main memory into a plurality of buffer uniquely identifiable within the address range of the predefined address word.
摘要翻译：一种用于启用大于相应虚拟存储器的物理存储器的方法和装置。公开了一种装置，其包括具有预定长度的地址字的处理器，具有大于预定义地址字的可寻址范围的大小的主存储器，以及用于配置处理器虚拟存储器以包含主存储器作为驻留存储器，并指向主存储器的剩余部分。公开了类似的方法步骤是将主存储器划分为在预定义地址字的地址范围内唯一可识别的多个缓冲器。

3. 发明授权

US5835775A Method and apparatus for executing a family generic processor specific application 失效
标题翻译：用于执行家庭通用处理器特定应用的方法和装置
公开(公告)号：US5835775A
公开(公告)日：1998-11-10
申请号：US764146
申请日：1996-12-12
申请人： Peter Washington , Richard R. Barton
发明人： Peter Washington , Richard R. Barton
IPC分类号： G06F9/06 , G06F9/455 , G06F9/44
CPC分类号： G06F9/45504
摘要： A method and computer system are disclosed for executing family generic, processor specific files. In accordance with one embodiment of the present invention, there is provided a method of executing a file on a computer system. The method includes the computer implemented steps of determining the processor type of a processor; storing a processor type identifier that represents the determined processor type of the processor; executing a first plurality of instructions that includes instructions exclusively from a common set of instructions that are common to a plurality of processor types; executing a second plurality of instructions that is optimized for a first processor type, if the processor type identifier indicates that the processor is of the first processor type; and executing a third plurality of instructions that includes instructions exclusively from the common set of instructions, if the processor type identifier indicates the processor is of a type different than the first processor type.
摘要翻译：公开了一种用于执行家庭通用处理器特定文件的方法和计算机系统。根据本发明的一个实施例，提供了一种在计算机系统上执行文件的方法。该方法包括计算机实现的步骤：确定处理器的处理器类型; 存储表示所确定的处理器的处理器类型的处理器类型标识符; 执行第一多个指令，其包括专用于多个处理器类型共有的公共指令集的指令; 如果处理器类型标识符指示处理器是第一处理器类型，则执行针对第一处理器类型而被优化的第二多个指令; 以及如果所述处理器类型标识符指示所述处理器的类型与所述第一处理器类型不同，则执行包括来自所述公共指令集的指令的第三多个指令。

4. 发明申请

US20210001509A1 APPARATUS AND METHOD FOR SPLITTING LOGS 有权
公开(公告)号：US20210001509A1
公开(公告)日：2021-01-07
申请号：US16918850
申请日：2020-07-01
申请人： Peter Washington
发明人： Peter Washington
IPC分类号： B27L7/00 , B27L7/06
摘要： One embodiment for splitting a log comprises a first handle; a second handle; a unitary body wedge comprising a cutting wedge coupled to the first handle and a splitting wedge coupled to the second handle, wherein the first handle and the second handle are co-aligned along an axis of the log splitting tool when the cutting wedge and the splitting wedge form the unitary body wedge. As a user swings the log splitting tool in an overhead arc, driving the unitary body wedge into a log that is to be split, a cutting edge of the cutting wedge is driven downward into the log. The user spreads the first and second handles apart in opposing directions so that leverage created by the length of the first and second handles force the cutting wedge and the splitting wedge to separate apart from each other, causing the log to split.

5. 发明授权

US11667046B2 Apparatus and method for splitting logs 有权
公开(公告)号：US11667046B2
公开(公告)日：2023-06-06
申请号：US16918850
申请日：2020-07-01
申请人： Peter Washington
发明人： Peter Washington
IPC分类号： B26B23/00 , B27L7/00 , B27L7/06
CPC分类号： B26B23/00 , B27L7/005 , B27L7/06
摘要： One embodiment for splitting logs is described as including a first handle; a second handle; a unitary body wedge comprising a cutting wedge coupled to the first handle and a splitting wedge coupled to the second handle, wherein the first handle and the second handle are co-aligned along an axis of the log splitting tool when the cutting wedge and the splitting wedge form the unitary body wedge. As a user swings the log splitting tool in an overhead arc, driving the unitary body wedge into a log that is to be split, a cutting edge of the cutting wedge is driven downward into the log. The user spreads the first and second handles apart in opposing directions so that leverage created by the length of the first and second handles force the cutting wedge and the splitting wedge to separate apart from each other, causing the log to split.

6. 发明授权

US6073225A Method and apparatus for monitoring bus transactions based on cycle type and memory address range 失效
标题翻译：基于周期类型和存储器地址范围监视总线事务的方法和装置
公开(公告)号：US6073225A
公开(公告)日：2000-06-06
申请号：US881414
申请日：1997-06-24
申请人： Larry C. James , Peter Washington
发明人： Larry C. James , Peter Washington
IPC分类号： G06F11/34 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F11/349 , G06F2201/87 , G06F2201/88 , G06F2201/885 , G06F2212/2542
摘要： Memory controller logic for concurrently obtaining memory access locality information by cycle type for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. The monitoring logic further includes a programmable cycle control register and comparison logic to condition the page access counters for specific memory cycle types, such as coherency cycles, reads, writes, copyback cache cycles, etc. Whenever the processing node generates a transaction requiring access to a memory address within system memory which matches the cycle type specified in the cycle control register, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns by cycle type is created which can be used to optimize memory and process assignments in the computer system.
摘要翻译：存储器控制器逻辑，用于为了优化包括分布式系统存储器的多节点NUMA架构计算机系统中的存储器和进程分配的目的而同时获得系统存储器（页）的大量连续部分的循环类型的存储器访问局部性信息。页面访问监视逻辑包含在包含共享系统存储器的一部分的每个处理节点内。该页面访问监视逻辑维护多个页面访问计数器，每个页面访问计数器对应于共享系统存储器内的不同存储器页面地址。监视逻辑还包括可编程周期控制寄存器和比较逻辑，用于对特定存储器周期类型（例如一致性周期，读取，写入，回拷缓存周期等）调节页面访问计数器。只要处理节点产生需要访问的事务系统存储器中与循环控制寄存器中指定的循环类型匹配的存储器地址，页面访问监视逻辑增加包含在寻址访问的存储器地址的页面访问计数器内的计数值。因此，创建了通过循环类型的存储器访问模式的记录，其可以用于优化计算机系统中的存储器和处理分配。

7. 发明申请

US20210001510A1 LOG SPLITTING DEVICE 有权
公开(公告)号：US20210001510A1
公开(公告)日：2021-01-07
申请号：US16921820
申请日：2020-07-06
申请人： Peter Washington
发明人： Peter Washington
IPC分类号： B27L7/06 , B27L7/00
摘要： A tool for log-splitting is provided with a handle structure defining a long axis, and including a first handle and a second handle. The handles extend substantially parallel to the long axis. Coupled to the handles are an axe head including a first wedge and a second wedge with the axe head extending perpendicularly from the long axis of the handle structure to a sharpened edge. The wedges are coupled by a hinged joint providing for the first and second wedges selectively to be aligned together and to be separated. The first wedge includes a notch behind the sharpened edge and the second wedge includes a leading edge that, with the wedges aligned together, is positioned in the notch.

8. 发明授权

US6026472A Method and apparatus for determining memory page access information in a non-uniform memory access computer system 失效
标题翻译：用于在不均匀的存储器访问计算机系统中确定存储器页面访问信息的方法和装置
公开(公告)号：US6026472A
公开(公告)日：2000-02-15
申请号：US881413
申请日：1997-06-24
申请人： Larry C. James , Arthur F. Cochcroft, Jr. , Peter Washington , Edward A. McDonald
发明人： Larry C. James , Arthur F. Cochcroft, Jr. , Peter Washington , Edward A. McDonald
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0813 , G06F2212/2542
摘要： A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.
摘要翻译：为了优化包括分布式系统存储器在内的多节点NUMA架构计算机系统中的存储器和处理分配的目的，同时获得用于系统存储器（页）的大量连续部分的存储器访问位置信息的硬件方法。页面访问监视逻辑包含在包含共享系统存储器的一部分的每个处理节点内。该页面访问监视逻辑维护多个页面访问计数器，每个页面访问计数器对应于共享系统存储器内的不同存储器页面地址。每当处理节点产生需要访问系统存储器内的存储器地址的事务时，页面访问监视逻辑增加与寻求访问的存储器地址相对应的页面访问计数器中的计数值。因此，创建了可用于优化计算机系统中的存储器和处理分配的存储器访问模式的记录。

9. 发明授权

US5860116A Memory page location control for multiple memory-multiple processor system 失效
标题翻译：多内存多处理器系统的内存页位置控制
公开(公告)号：US5860116A
公开(公告)日：1999-01-12
申请号：US764400
申请日：1996-12-11
申请人： Peter Washington
发明人： Peter Washington
IPC分类号： G06F15/16 , G06F9/50 , G06F12/06 , G06F12/08 , G06F12/12 , G06F12/02
CPC分类号： G06F9/5016 , G06F12/08 , G06F12/122 , G06F9/4856
摘要： An apparatus and method for controlling the location of pages in a system having multiple processors and multiple main memory. Local and remote accesses to main memory are monitored and when remote accesses exceed local accesses in a predefined period, steps to alleviate the volume of remote accesses are undertaken. The steps may result in the relocation of a memory page, replication of a memory page (for read only pages) and relocation of a process.
摘要翻译：一种用于控制具有多个处理器和多个主存储器的系统中的页面位置的装置和方法。监视对主存储器的本地和远程访问，并且当远程访问在预定时间段内超出本地访问时，进行减轻远程访问量的步骤。这些步骤可能会导致内存页面的重定位，内存页面的复制（只读页面）和进程的重定位。

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