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1. 发明授权

US07414281B1 Flash memory with high-K dielectric material between substrate and gate 有权
标题翻译：闪存与衬底和栅极之间的高K电介质材料
公开(公告)号：US07414281B1
公开(公告)日：2008-08-19
申请号：US10658936
申请日：2003-09-09
申请人： Richard M. Fastow , Yue-Song He , Zhigang Wang
发明人： Richard M. Fastow , Yue-Song He , Zhigang Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/513 , H01L29/7881
摘要： A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.
摘要翻译：描述闪存单元及其形成方法。闪速存储单元可以包括在衬底和栅极元件之间具有源极和漏极的衬底，栅极元件和介电层。电介质层包括介电常数大于二氧化硅的电介质材料。

2. 发明授权

US06867119B2 Nitrogen oxidation to reduce encroachment 有权
标题翻译：氮氧化减少侵蚀
公开(公告)号：US06867119B2
公开(公告)日：2005-03-15
申请号：US10284866
申请日：2002-10-30
申请人： Yue-Song He , Richard M. Fastow , Zhi-Gang Wang
发明人： Yue-Song He , Richard M. Fastow , Zhi-Gang Wang
IPC分类号： H01L21/28 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66825 , H01L21/28247 , H01L21/28273
摘要： A method of manufacturing a metal oxide semiconductor. A gate structure of the metal oxide semiconductor is etched. A nitrogen-comprising gas, which may be NO or N2O, is made to flow over the metal oxide semiconductor. A pre-implant film is grown over the edges of the gate structure. The pre-implant film may repair damage to a gate stack edge caused by an etching process. The film may be substantially silicon nitride. Beneficially, such a film may be thinner than a conventional silica oxide film. A thinner film does not deleteriously contribute to non-uniformities in a tunnel oxide. A non-uniform tunnel oxide may result in a non-uniform field between a gate and a channel. Non-uniform fields may have numerous deleterious effects. Advantageously, embodiments of the present invention overcome prior art deficiencies in repairing gate stack edge defects. In this novel manner, gate stack edge defects may be physically repaired without deleterious consequences to the electrical behavior of a metal oxide semiconductor device. The novel application of silicon nitride to this application allows thin repair layers to be grown. Advantageously, semiconductors manufactured using embodiments of the present invention may utilize smaller process feature sizes, resulting in denser arrays of semiconductor devices, resulting in lower costs for such devices and realizing a competitive advantage to practitioners of the improvements in the arts herein described.
摘要翻译：一种制造金属氧化物半导体的方法。蚀刻金属氧化物半导体的栅极结构。使含氮气体（可以是NO或N 2 O）流过金属氧化物半导体。在门结构的边缘上生长预植入膜。预植入膜可以修复由蚀刻工艺引起的栅堆叠边缘的损坏。该膜可以基本上是氮化硅。有利地，这种膜可以比常规二氧化硅膜薄。更薄的膜对隧道氧化物中的不均匀性没有有害的贡献。不均匀隧道氧化物可能导致栅极和沟道之间的不均匀场。非均匀场可能有许多有害影响。有利地，本发明的实施例克服了修复栅极堆叠边缘缺陷的现有技术缺陷。以这种新颖的方式，可以物理地修复栅极堆叠边缘缺陷，而不会对金属氧化物半导体器件的电气行为产生有害影响。氮化硅在该应用中的新颖应用允许生长薄的修复层。有利地，使用本发明的实施例制造的半导体可以利用较小的工艺特征尺寸，导致更密集的半导体器件阵列，从而导致这些器件的成本降低，并且对于本领域技术人员的改进实现了竞争优势。

3. 发明授权

US06833297B1 Method for reducing drain induced barrier lowering in a memory device 有权
标题翻译：用于减少存储器件中的漏极引起的屏障降低的方法
公开(公告)号：US06833297B1
公开(公告)日：2004-12-21
申请号：US10265001
申请日：2002-10-04
申请人： Richard M. Fastow , Yue-Song He , Nga-Ching Wong
发明人： Richard M. Fastow , Yue-Song He , Nga-Ching Wong
IPC分类号： H01L218234
CPC分类号： H01L29/66825 , H01L29/7883
摘要： The present invention is a method for fabricating a memory device. In one embodiment, a first impurity concentration is deposited in a channel region of a memory device. A second impurity concentration, which overlies the first impurity concentration, is then created in the channel region. Finally, a memory array is fabricated upon the channel region. The memory array overlies the first impurity concentration and the second impurity concentration.
摘要翻译：本发明是一种用于制造存储器件的方法。在一个实施例中，第一杂质浓度沉积在存储器件的沟道区中。然后在通道区域中产生第二杂质浓度，其覆盖第一杂质浓度。最后，在通道区域上制造存储器阵列。存储器阵列覆盖第一杂质浓度和第二杂质浓度。

4. 发明授权

US07020021B1 Ramped soft programming for control of erase voltage distributions in flash memory devices 有权
标题翻译：用于控制闪存器件中擦除电压分布的斜坡软编程
公开(公告)号：US07020021B1
公开(公告)日：2006-03-28
申请号：US10981833
申请日：2004-11-04
申请人： Wing-Han Leung , Richard M. Fastow , Yue-Song He , Sheung-Hee Park
发明人： Wing-Han Leung , Richard M. Fastow , Yue-Song He , Sheung-Hee Park
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/3445 , G11C16/3468 , G11C16/3477
摘要： A method of erasing bits in a multi-level cell flash memory array is described. The method includes applying over-erase verification after each erase pulse. If cells verify as over-erased, a ramped over-erase correction pulse is applied. The voltage of each over-erase correction pulse is incrementally greater than the previous pulse, until all bits in all cells pass the over-erase verification. In this way, the widths of the threshold voltage distributions of the erased bits are kept to a minimum.
摘要翻译：描述了擦除多级单元闪存阵列中的位的方法。该方法包括在每个擦除脉冲之后应用过擦除验证。如果电池验证为过擦除，则施加斜坡过擦除校正脉冲。每个过擦除校正脉冲的电压递增地大于先前的脉冲，直到所有单元中的所有位通过过擦除验证。以这种方式，擦除位的阈值电压分布的宽度保持最小。

5. 发明授权

US06939766B1 Method for fabricating a flash memory device 有权
标题翻译：闪存器件的制造方法
公开(公告)号：US06939766B1
公开(公告)日：2005-09-06
申请号：US10616804
申请日：2003-07-09
申请人： Yue-Song He , Richard M. Fastow , Jianshi Wang
发明人： Yue-Song He , Richard M. Fastow , Jianshi Wang
IPC分类号： H01L21/28 , H01L21/8247
CPC分类号： H01L21/28273
摘要： The present invention is a method for fabricating a flash memory device. In one embodiment, a gate structure comprising a tunnel oxide layer, a floating gate layer, an oxide layer, and a control gate layer is fabricated on a semiconductor substrate. A rapid thermal oxidation (RTO) process is then performed to repair the tunnel oxide layer.
摘要翻译：本发明是一种制造闪存装置的方法。在一个实施例中，在半导体衬底上制造包括隧道氧化物层，浮动栅极层，氧化物层和控制栅极层的栅极结构。然后进行快速热氧化（RTO）处理以修复隧道氧化物层。

6. 发明授权

US06894925B1 Flash memory cell programming method and system 有权
标题翻译：闪存单元编程方法和系统
公开(公告)号：US06894925B1
公开(公告)日：2005-05-17
申请号：US10342585
申请日：2003-01-14
申请人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
发明人： Sheunghee Park , Sameer S. Haddad , Chi Chang , Richard M. Fastow , Ming Sang Kwan , Zhigang Wang
IPC分类号： G11C11/56 , G11C16/04 , H01L29/423 , H01L29/788
CPC分类号： G11C11/5621 , G11C16/0416 , H01L29/42324 , H01L29/7883
摘要： A flash memory cell programming system and method that facilitate efficient and quick operation of a flash memory cell by providing a biasable well (e.g., substrate) is presented. The biasable well flash memory cell enables increases in electrical field strengths in a manner that eases resistance to charge penetration of a dielectric barrier (e.g., oxide) around a charge trapping region (e.g., a floating gate). The present biasable well system and method also create a self convergence point that increase control during programming operations and reduces the chances of excessive correction for over erased memory cells. The biasing can assist hard programming to store information and/or soft programming to correct the effects of over-erasing. The biasing can also reduce stress on a drain voltage pump, reduce leakage current and reduce programming durations. Some implementations also include a biasable control gate component, biasable source component and biasable drain component.
摘要翻译：提出了一种闪存单元编程系统和方法，其通过提供可偏置的阱（例如，衬底）来促进闪存单元的有效和快速的操作。可偏置阱快闪存储器单元能够以减轻电荷俘获区域（例如浮栅）周围的电介质势垒（例如氧化物）的电荷穿透的方式增加电场强度。本发明的偏压井系统和方法还创建了一个自会聚点，从而在编程操作期间增加了控制，并降低了对擦除过的存储器单元过度校正的可能性。偏置可以帮助硬编程来存储信息和/或软编程以校正过度擦除的影响。偏置还可以减少漏极电压泵上的应力，减少泄漏电流并减少编程持续时间。一些实施方案还包括可偏置控制栅极分量，可偏置源分量和可偏置漏极分量。

7. 发明授权

US06477083B1 Select transistor architecture for a virtual ground non-volatile memory cell array 失效
标题翻译：选择用于虚拟地面非易失性存储单元阵列的晶体管架构
公开(公告)号：US06477083B1
公开(公告)日：2002-11-05
申请号：US09686685
申请日：2000-10-11
申请人： Richard M. Fastow , Mark W. Randolph , Shane C. Hollmer
发明人： Richard M. Fastow , Mark W. Randolph , Shane C. Hollmer
IPC分类号： G11C1604
CPC分类号： H01L27/11568 , G11C16/0475 , G11C16/0491 , G11C16/14 , H01L27/115
摘要： A bit line selector for a virtual ground non-volatile read only memory (“NROM”) cell array is disclosed. The selector transistors are oriented such that the channel length is perpendicular to the bit line and the channel width is parallel to the bit line. Subsequent reduction in the bit line pitch does not affect the channel width of the select transistors or their drive current.
摘要翻译：公开了用于虚拟非易失性只读存储器（“NROM”）单元阵列的位线选择器。选择器晶体管被定向成使得沟道长度垂直于位线并且沟道宽度平行于位线。位线间距的随后减小不会影响选择晶体管的沟道宽度或其驱动电流。

8. 发明授权

US06819615B1 Memory device having resistive element coupled to reference cell for improved reliability 有权
标题翻译：具有耦合到参考电池的电阻元件以提高可靠性的存储器件
公开(公告)号：US06819615B1
公开(公告)日：2004-11-16
申请号：US10285909
申请日：2002-10-31
申请人： Richard M. Fastow , Wing Han Leung , John Wang
发明人： Richard M. Fastow , Wing Han Leung , John Wang
IPC分类号： G11C702
CPC分类号： G11C16/28 , G11C7/14
摘要： A reference cell transistor with a series resistance to improve reliability in reading cells in an associated memory array. The reference cell transistor is coupled in series with a resistive element such that a reference current flows therethrough to reduce a voltage between a gate and a source of the reference cell transistor. This bends the Ids versus Vgate curve of the reference cell downward and compensates for irregularities in the resistance seen in series with the memory cell transistors. In this fashion, the margin when reading memory cells is improved and the reference current is more reliable. The resistive element may be external to a region having the reference cell transistor. Alternatively, the resistive element may be internal to a region with the memory array and reference cell. For example, it may be formed by extending the source region of the reference cell transistor.
摘要翻译：具有串联电阻的参考单元晶体管，以提高在相关存储器阵列中读取单元的可靠性。参考单元晶体管与电阻元件串联耦合，使得参考电流流过其中以降低参考单元晶体管的栅极和源极之间的电压。这将向下弯曲参考单元的Ids与Vgate曲线，并补偿与存储单元晶体管串联看到的电阻的不规则性。以这种方式，读取存储单元时的余量得到改善，并且参考电流更可靠。电阻元件可以在具有参考单元晶体管的区域的外部。或者，电阻元件可以在具有存储器阵列和参考单元的区域内部。例如，可以通过延长参考单元晶体管的源极区域而形成。

9. 发明授权

US06438031B1 Method of programming a non-volatile memory cell using a substrate bias 有权
标题翻译：使用衬底偏置来编程非易失性存储单元的方法
公开(公告)号：US06438031B1
公开(公告)日：2002-08-20
申请号：US09697815
申请日：2000-10-26
申请人： Richard M. Fastow
发明人： Richard M. Fastow
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C16/0475
摘要： A memory cell that includes a substrate that has a first region and a second region with a channel therebetween. The memory cell further includes a gate above the channel and a charge trapping region that contains a first amount of charge, wherein the first region is doped to such an extent that electric fields are reduced at the locations in the substrate where impact ionization occurs during programming.
摘要翻译：一种存储单元，其包括具有第一区域的基板和在其间具有通道的第二区域。存储单元还包括通道上方的栅极和包含第一电荷量的电荷捕获区域，其中第一区域被掺杂到在编程期间发生冲击电离的基板中的位置处的电场减小的程度。

10. 发明授权

US07217964B1 Method and apparatus for coupling to a source line in a memory device 有权
标题翻译：用于耦合到存储器件中的源极线的方法和装置
公开(公告)号：US07217964B1
公开(公告)日：2007-05-15
申请号：US10658937
申请日：2003-09-09
申请人： Richard M. Fastow , Kuo-Tung Chang
发明人： Richard M. Fastow , Kuo-Tung Chang
IPC分类号： H01L27/10
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： A method and apparatus for coupling to a source line. Specifically, embodiments of the present invention disclose a memory device comprising an array of flash memory cells with a source line connection that facilitates straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column implanted with n-type dopants is also isolated between an adjoining pair of STI regions. The source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions in the array. A source contact is coupled to the source column for providing electrical coupling with the plurality of source regions. The source contact is located along a row of drain contacts that are coupled to drain regions of a row of memory cells.
摘要翻译：一种用于耦合到源极线的方法和装置。具体地，本发明的实施例公开了一种包括具有促进直线字线的源极线连接的闪存单元阵列的存储器件及其制造方法。阵列由隔离多个存储单元列的多个不相交的浅沟槽隔离（STI）区域组成。植入n型掺杂剂的源极柱也在相邻的一对STI区域之间隔离。源极列耦合到耦合到阵列中的多个源极区域的多个公共源极线。源极触点耦合到源极列，以提供与多个源极区域的电耦合。源极触点沿着一排漏极触点排列，这些漏极触点被耦合到一行存储器单元的漏极区域。

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