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1. 发明授权

US5801095A Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology 失效
标题翻译：深层次半微米后端技术的生产价值互连过程
公开(公告)号：US5801095A
公开(公告)日：1998-09-01
申请号：US710071
申请日：1996-09-10
申请人： Richard J. Huang , Christy M.-C. Woo
发明人： Richard J. Huang , Christy M.-C. Woo
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L29/45 , H01L21/28
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76841 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L29/456 , H01L2924/0002 , Y10S257/915
摘要： The present invention is directed to improving the throughput of the process for fabricating multilayer interconnects. Tungsten plugs, formed in contact/via openings etched in an interlayer dielectric, have been widely used in industry to form interconnection between different metal layers. An adhesion layer comprising a Ti/TiN stack is typically employed to support the adhesion of the tungsten plug in the contact/via openings. The present invention is directed to a process involving the formation of a Ti/TiN landing pad at the base of contact/via openings prior to the deposition of the interlayer dielectric. The process of the present invention enables the removal of the Ti under-layer and the reduction of the TiN thickness in the Ti/TiN stack. The throughput of the process for fabricating multilayer interconnects is thus greatly improved while the integrity of the devices are maintained.
摘要翻译：本发明旨在改进用于制造多层互连的工艺的生产量。形成在层间电介质中蚀刻的接触/通孔开口的钨塞已被广泛用于工业中以形成不同金属层之间的互连。通常使用包含Ti / TiN叠层的粘合层来支撑钨丝塞在接触/通孔中的粘附。本发明涉及在沉积层间电介质之前在接触/通孔开口的底部形成Ti / TiN着陆焊盘的方法。本发明的方法能够在Ti / TiN叠层中除去Ti底层和TiN厚度的降低。因此，在保持装置的完整性的同时，大大提高了用于制造多层互连的工艺的生产量。

2. 发明授权

US5686761A Production worthy interconnect process for deep sub-half micrometer back-end-of-line technology 失效
标题翻译：深层次半微米后端技术的生产价值互连过程
公开(公告)号：US5686761A
公开(公告)日：1997-11-11
申请号：US608913
申请日：1996-02-29
申请人： Richard J. Huang , Christy M.-C. Woo
发明人： Richard J. Huang , Christy M.-C. Woo
IPC分类号： H01L21/768 , H01L23/485 , H01L23/522 , H01L29/45 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76843 , H01L21/7684 , H01L21/76841 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L29/456 , H01L2924/0002 , Y10S257/915
摘要： The present invention is directed to improving the throughput of the process for fabricating multilayer interconnects. Tungsten plugs, formed in contact/via openings etched in an interlayer dielectric, have been widely used in industry to form interconnection between different metal layers. An adhesion layer comprising a Ti/TiN stack is typically employed to support the adhesion of the tungsten plug in the contact/via openings. The present invention is directed to a process involving the formation of a Ti/TiN landing pad at the base of contact/via openings prior to the deposition of the interlayer dielectric. The process of the present invention enables the removal of the Ti under-layer and the reduction of the TiN thickness in the Ti/TiN stack. The throughput of the process for fabricating multilayer interconnects is thus greatly improved while the integrity of the devices are maintained.
摘要翻译：本发明旨在改进用于制造多层互连的工艺的生产量。形成在层间电介质中蚀刻的接触/通孔开口的钨塞已被广泛用于工业中以形成不同金属层之间的互连。通常使用包含Ti / TiN叠层的粘合层来支撑钨丝塞在接触/通孔中的粘附。本发明涉及在沉积层间电介质之前在接触/通孔开口的底部形成Ti / TiN着陆焊盘的方法。本发明的方法能够在Ti / TiN叠层中除去Ti底层和TiN厚度的降低。因此，在保持装置的完整性的同时，大大提高了用于制造多层互连的工艺的生产量。

3. 发明申请

US20120007221A1 MASK FOR FORMING INTEGRATED CIRCUIT 有权
标题翻译：形成集成电路的掩模
公开(公告)号：US20120007221A1
公开(公告)日：2012-01-12
申请号：US13241810
申请日：2011-09-23
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L29/66 , C23F1/00
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

4. 发明授权

US07521304B1 Method for forming integrated circuit 失效
标题翻译：集成电路形成方法
公开(公告)号：US07521304B1
公开(公告)日：2009-04-21
申请号：US10230775
申请日：2002-08-29
申请人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Scott A. Bell , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Richard C. Nguyen , Cyrus E. Tabery , Lu You
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/0332 , H01L21/28035 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.
摘要翻译：形成集成电路的方法包括在导电材料层之上提供包括电介质材料的缓冲层，并在缓冲层上方提供一层掩模材料。掩模材料包括无定形碳。该方法还包括去除缓冲层的一部分和掩模材料层以形成掩模。根据掩模在导电材料层中形成特征。

5. 发明授权

US06518646B1 Semiconductor device with variable composition low-k inter-layer dielectric and method of making 有权
标题翻译：具有可变组成的低k层间电介质的半导体器件及其制造方法
公开(公告)号：US06518646B1
公开(公告)日：2003-02-11
申请号：US09819615
申请日：2001-03-29
申请人： Dawn M. Hopper , Suzette K. Pangrle , Calvin T. Gabriel , Richard J. Huang , Lu You
发明人： Dawn M. Hopper , Suzette K. Pangrle , Calvin T. Gabriel , Richard J. Huang , Lu You
IPC分类号： H01L2358
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76807 , H01L21/76822 , H01L21/76829 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Strong adhesion to doped low-k inter-layer dielectrics is provided by varying the composition of dopant near the surface layers of the inter-layer dielectric. The concentration of dopant is gradually increased from about zero atomic % at the interface between the inter-layer dielectric and semiconductor substrate to improve adhesion of the inter-layer dielectric to the semiconductor substrate. The concentration of dopant at the upper surface of the inter-layer dielectric is gradually decreased to about zero atomic % at the upper surface of the inter-layer dielectric film in order to improve adhesion of additional layers to the inter-layer dielectric.
摘要翻译：通过改变层间电介质的表面层附近掺杂剂的组成，提供了对掺杂低k层间电介质的强粘合性。掺杂剂的浓度在层间电介质和半导体衬底之间的界面处从约零原子％逐渐增加，以提高层间电介质与半导体衬底的粘合性。层间电介质的上表面的掺杂剂浓度在层间电介质膜的上表面逐渐降低至约零原子％，以提高附加层对层间电介质的附着力。

6. 发明授权

US06317642B1 Apparatus and methods for uniform scan dispensing of spin-on materials 有权
标题翻译：用于均匀扫描分配旋涂材料的装置和方法
公开(公告)号：US06317642B1
公开(公告)日：2001-11-13
申请号：US09191438
申请日：1998-11-12
申请人： Lu You , Dawn Hopper , Christof Streck , John Pellerin , Richard J. Huang
发明人： Lu You , Dawn Hopper , Christof Streck , John Pellerin , Richard J. Huang
IPC分类号： G06F1900
CPC分类号： H01L21/6715 , B05D1/005
摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of deposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.
摘要翻译：本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。改进的装置提供沉积室内的受控温度，压力和气体组成。改进的方法包括通过可移动的分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液沉积在晶片上的图案。本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。在一个实施方案中，前体溶液从晶片的外边缘向中心分配。在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

7. 发明授权

US06235453B1 Low-k photoresist removal process 有权
标题翻译：低k光刻胶去除工艺
公开(公告)号：US06235453B1
公开(公告)日：2001-05-22
申请号：US09349055
申请日：1999-07-07
申请人： Lu You , Steven C. Avanzino , Jacques Bertrand , Richard J. Huang
发明人： Lu You , Steven C. Avanzino , Jacques Bertrand , Richard J. Huang
IPC分类号： G03F726
CPC分类号： G03F7/427 , G03F7/42 , H01L21/02052 , H01L21/31138
摘要： An integrated circuit and a method of removing photoresist is described. The process described uses a low oxygen gas or non-oxygen gas plasma that removes the photoresist and provides a protective surface layer over the low-k dielectric material. The low-k dielectric material is part of a dielectric stack. After exposure to the gas plasmas the integrated circuit is subjected to solvent.
摘要翻译：描述了集成电路和去除光致抗蚀剂的方法。所描述的方法使用低氧气体或非氧气体等离子体，其去除光致抗蚀剂并在低k电介质材料上提供保护性表面层。低k电介质材料是电介质叠层的一部分。暴露于气体等离子体后，集成电路经受溶剂。

8. 发明授权

US06225240B1 Rapid acceleration methods for global planarization of spin-on films 有权
标题翻译：用于旋涂膜全局平面化的快速加速方法
公开(公告)号：US06225240B1
公开(公告)日：2001-05-01
申请号：US09191101
申请日：1998-11-12
申请人： Lu You , Dawn Hopper , Richard J. Huang
发明人： Lu You , Dawn Hopper , Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/02134 , B05D1/005 , H01L21/02282 , H01L21/31051 , H01L21/312 , H01L21/3124 , H01L21/3127
摘要： This invention describes improved apparatus and methods for spin-on deposition of semiconductor thin films. The improved apparatus provides for controlled temperature, pressure and gas compositions within the deposition chamber. The improved methods comprise dispensing of solutions containing thin film precursor via a moveable dispensing device and the careful regulation of the pattern of desposition of the precursor solution onto the wafer. The invention also comprises the careful regulation of deposition variables including dispensation time, wafer rpm, stop time and rates of wafer rotation. In one embodiment, the precursor solution is dispensed from the outer edge of the wafer toward the center. In alternative embodiments, processors regulate the movement of the dispensing arm and the precursor pump to provide an evenly dispensed layer of precursor solution. The invention also describes improved methods for evaporating solvents and curing thin films. The methods of this invention enable the production of spin-on thin films, which have more even film thickness and uniformity. The semiconductor thin films produced by the methods of this invention are useful for the manufacture of semiconductor devices comprising interlevel dielectric materials.
摘要翻译：本发明描述了用于半导体薄膜的旋涂沉积的改进的装置和方法。改进的装置提供沉积室内的受控温度，压力和气体组成。改进的方法包括通过可移动分配装置分配含有薄膜前体的溶液，以及仔细调节前体溶液在晶片上的排列方式。本发明还包括仔细调节沉积变量，包括分配时间，晶片转速，停止时间和晶片旋转速率。在一个实施方案中，前体溶液从晶片的外边缘向中心分配。在替代实施例中，处理器调节分配臂和前驱泵的运动，以提供均匀分配的前体溶液层。本发明还描述了用于蒸发溶剂和固化薄膜的改进方法。本发明的方法能够生产具有更均匀的膜厚度和均匀性的旋涂薄膜。通过本发明的方法生产的半导体薄膜可用于制造包括层间电介质材料的半导体器件。

9. 发明授权

US06133619A Reduction of silicon oxynitride film delamination in integrated circuit inter-level dielectrics 有权
标题翻译：集成电路级间介质中氮氧化硅薄膜的分层还原
公开(公告)号：US06133619A
公开(公告)日：2000-10-17
申请号：US144521
申请日：1998-08-31
申请人： Kashmir Sahota , Richard J. Huang , David Matsumoto , Mark T. Ramsbey , Yu Sun , Judith Quan Rizzuto
发明人： Kashmir Sahota , Richard J. Huang , David Matsumoto , Mark T. Ramsbey , Yu Sun , Judith Quan Rizzuto
IPC分类号： H01L21/312 , H01L21/314 , H01L21/768 , H01L51/00
CPC分类号： H01L21/76801 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/3124 , H01L21/3145
摘要： Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned conductive layer during subsequent thermal processing are avoided or significantly reduced by controlling the thickness of the dielectric cap layer on the dielectric gap fill layer. Embodiments include depositing a conformal SiON barrier on a first conductive pattern, depositing a HSQ gap fill layer on the conformal SiON barrier layer, depositing a silicon oxide cap layer and planarizing such that the thickness of the planarized silicon cap layer is at least 2500 .ANG., thereby avoiding deformation and/or delamination of a conformal SiON barrier layer on an overlying patterned conductive layer during subsequent thermal processing.
摘要翻译：从介电间隙填充层，例如低介电常数材料（例如HSQ）以及随后的热处理过程中覆盖的图案化导电层上的阻挡介电层的伴随变形或分层的脱气被避免或显着减少，通过控制电介质间隙填充层上的介电覆盖层。实施例包括在第一导电图案上沉积保形SiON阻挡层，在保形SiON阻挡层上沉积HSQ间隙填充层，沉积氧化硅覆盖层并进行平坦化，使得平坦化硅覆盖层的厚度为至少2500，从而避免在随后的热处理期间覆盖的图案化导电层上的保形SiON阻挡层的变形和/或分层。

10. 发明授权

US6093635A High integrity borderless vias with HSQ gap filled patterned conductive layers 失效
标题翻译：高完整性无边界通孔与HSQ间隙填充图案导电层
公开(公告)号：US6093635A
公开(公告)日：2000-07-25
申请号：US993124
申请日：1997-12-18
申请人： Khanh Tran , Richard J. Huang , Simon S. Chan , Lu You
发明人： Khanh Tran , Richard J. Huang , Simon S. Chan , Lu You
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L21/76828 , Y10S438/958
摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.
摘要翻译：无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

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