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1. 发明授权

US5467370A Method and apparatus for an adaptive three tap transversal equalizer for partial-response signaling 失效
标题翻译：用于部分响应信号的自适应三抽头横向均衡器的方法和装置
公开(公告)号：US5467370A
公开(公告)日：1995-11-14
申请号：US217493
申请日：1994-03-24
申请人： Richard G. Yamasaki , Tzu-Wang Pan
发明人： Richard G. Yamasaki , Tzu-Wang Pan
IPC分类号： H03H21/00 , G11B20/10 , H03H15/00 , H03H17/00 , H03M13/23 , H03M13/39 , H04B3/04 , H03H7/30 , G11B5/035
CPC分类号： G11B20/10009
摘要： An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm. In systems employing separate adaptive loops for gain control, timing recovery and equalization, the amount of undesired loop interaction is much reduced from that of prior art methods.
摘要翻译：一种用于部分响应信号的改进的自适应三抽头横向均衡器。本发明降低了硬件的复杂性，同时降低了均衡器对增益和定时误差的敏感性。本发明采用基于零附近的样本值的算法。由此导致的误差的平均幅度的降低导致对增益误差的敏感性降低。本发明的算法改进了采样定时误差的消除。在本发明中，通过随机梯度的积分来更新自适应余弦均衡器的系数。为了计算梯度，将来自先前样本的量化输出和当前样本的输出的乘积与来自先前样本的输出和当前样本的量化输出的乘积相加。另外，均衡器输出被屏蔽，使得量化到非零值的值在更新算法中被丢弃。在采用单独的自适应环路用于增益控制，定时恢复和均衡的系统中，与现有技术方法相比，不期望的环路相互作用量大大降低。

2. 发明授权

US5644595A Method and apparatus for an adaptive three tap transversal equalizer for partial-response signaling 失效
标题翻译：用于部分响应信号的自适应三抽头横向均衡器的方法和装置
公开(公告)号：US5644595A
公开(公告)日：1997-07-01
申请号：US456654
申请日：1995-06-02
申请人： Richard G. Yamasaki , Tzu-Wang Pan
发明人： Richard G. Yamasaki , Tzu-Wang Pan
IPC分类号： H03H21/00 , G11B20/10 , H03H15/00 , H03H17/00 , H03M13/23 , H03M13/39 , H04B3/04 , H03H7/30 , G11B5/035
CPC分类号： G11B20/10009
摘要： An improved adaptive three tap transversal equalizer for partial-response signaling. The invention reduces the complexity of the hardware, as well as reducing the sensitivity of the equalizer to gain and timing errors. The present invention employs an algorithm based on sample values around zero. The resulting decrease in average magnitude of the error results in decreased sensitivity to gain errors. The algorithm of the present invention improves cancellation of sample timing errors. In the present invention, the coefficient of an adaptive cosine equalizer is updated by integration of a stochastic gradient. To calculate the gradient, the product of the quantized output from the previous sample and the output from the present sample is summed together with the product of the output from the previous sample and the quantized output from the present sample. In addition, the equalizer output is masked such that values quantizing to non-zero values are discarded in the update algorithm. In systems employing separate adaptive loops for gain control, timing recovery and equalization, the amount of undesired loop interaction is much reduced from that of prior art methods.
摘要翻译：一种用于部分响应信号的改进的自适应三抽头横向均衡器。本发明降低了硬件的复杂性，同时降低了均衡器对增益和定时误差的敏感性。本发明采用基于零附近的样本值的算法。由此导致的误差的平均幅度的降低导致对增益误差的敏感性降低。本发明的算法改进了采样定时误差的消除。在本发明中，通过随机梯度的积分来更新自适应余弦均衡器的系数。为了计算梯度，将来自先前样本的量化输出和当前样本的输出的乘积与来自先前样本的输出和当前样本的量化输出的乘积相加。另外，均衡器输出被屏蔽，使得量化到非零值的值在更新算法中被丢弃。在采用单独的自适应环路用于增益控制，定时恢复和均衡的系统中，与现有技术方法相比，不期望的环路相互作用量大大降低。

3. 发明授权

US5311178A Method for processing sample values in an RLL channel 失效
标题翻译：用于处理RLL通道中样本值的方法
公开(公告)号：US5311178A
公开(公告)日：1994-05-10
申请号：US930718
申请日：1992-08-14
申请人： Tzu-Wang Pan , Richard G. Yamasaki
发明人： Tzu-Wang Pan , Richard G. Yamasaki
IPC分类号： G11B20/10 , G11B20/14 , H03L7/06 , H04L7/033 , G11B5/09
CPC分类号： G11B20/10055 , G11B20/10009 , G11B20/1403 , H04L7/0334
摘要： The present invention describes an improved RLL channel utilizing a closed-loop clock recovery scheme and a simplified decoding algorithm. (1,7) run-length-limited (RLL) code is used to reduce the magnetic nonlinearity problem posed by prior art PRML systems. In the preferred embodiment of the present invention, the analog data signal amplified, filtered and equalized to approximate an ideal waveform. The signal is then sampled and decoded into binary data. The clock recovery circuit is designed to sample the analog data such that the signal peak lies centered between consecutive sample points. It is thus made possible for the phase error to be extracted from a direct comparison of neighboring sample values. The phase error is then used to adjust the clock signal for the following samples. In the decoding algorithm of the present invention, by making useful approximations, the complexity of the decision functions is reduced, along with the number of required look-ahead samples. The reduction in look-ahead samples reduces the system's sensitivity to misequalization.
摘要翻译：本发明描述了利用闭环时钟恢复方案和简化的解码算法的改进的RLL信道。（1,7）游程限制（RLL）代码用于减少由现有技术的PRML系统构成的磁性非线性问题。在本发明的优选实施例中，模拟数据信号被放大，滤波和均衡以接近理想波形。然后将信号采样并解码成二进制数据。时钟恢复电路被设计为对模拟数据进行采样，使得信号峰位于连续采样点之间的中心。因此，可以从相邻采样值的直接比较中提取相位误差。然后，相位误差用于调整以下样本的时钟信号。在本发明的解码算法中，通过进行有用的近似，减少了决定函数的复杂度以及所需要的先行样本的数量。预测样本的减少降低了系统对门槛资格的敏感性。

4. 发明授权

US5917859A Method and apparatus for implementing a viterbi detector for PRML channels 失效
标题翻译：用于实现PRML通道的维特比检测器的方法和装置
公开(公告)号：US5917859A
公开(公告)日：1999-06-29
申请号：US893863
申请日：1997-07-11
申请人： Richard G. Yamasaki , Tzu-Wang Pan
发明人： Richard G. Yamasaki , Tzu-Wang Pan
IPC分类号： G11B20/14 , G11B20/10 , G11B20/18 , H03L7/06 , H04L25/08 , H04L25/497 , H04L27/28 , H04L5/12
CPC分类号： G11B20/10009
摘要： An improved Viterbi detector for use in a partial-response maximum-likelihood (PRML) channel. The present invention reduces the amount of hardware necessary in the conventional digital implementation, as well as increasing the speed of the system, by utilizing analog circuits. Whereas prior art analog implementations use more complex hardware and less efficient algorithms, the present invention utilizes easily realizable circuitry to perform a more efficient algorithm. A sampled data Viterbi detector compares a sampled analog input signal with two threshold signals. The binary outputs of the comparing means are then provided to a survival sequence register, as well as being used to formulate new threshold signals for the subsequent input sample. The hardware implements Ferguson's method for calculating sequence metrics by representing the accumulated metric difference as two threshold signals. Probability based decisions are then performed in analog comparators. Because Ferguson's method only requires formulation of the difference between metrics rather than formulation of the true metrics themselves, the successive threshold signals that represent this difference can be generated using multi-input track and hold circuits and a voltage summing means.
摘要翻译：用于部分响应最大似然（PRML）信道的改进的维特比检测器。本发明通过利用模拟电路来减少传统数字实现中所需的硬件数量以及增加系统的速度。而现有技术的模拟实现使用更复杂的硬件和较低效率的算法，本发明利用易于实现的电路来执行更有效的算法。采样数据维特比检测器将采样的模拟输入信号与两个阈值信号进行比较。然后将比较装置的二进制输出提供给生存序列寄存器，以及用于为随后的输入样本制定新的阈值信号。硬件通过将累积度量差表示为两个阈值信号来实现Ferguson的计算顺序度量的方法。然后在模拟比较器中执行基于概率的决策。因为弗格森的方法只需要制定度量之间的差异，而不是制定真实度量本身，所以可以使用多输入跟踪和保持电路以及电压求和装置来产生代表该差异的连续阈值信号。

5. 发明授权

US4800340A Method and apparatus for generating a data recovery window 失效
标题翻译：用于生成数据恢复窗口的方法和装置
公开(公告)号：US4800340A
公开(公告)日：1989-01-24
申请号：US41728
申请日：1987-04-22
申请人： Peter Maimone , Richard G. Yamasaki
发明人： Peter Maimone , Richard G. Yamasaki
IPC分类号： H03K3/017 , H03K3/282 , H04L7/033 , H03L7/00
CPC分类号： H03K3/2821 , H03K3/017 , H04L7/033
摘要： Method and apparatus for generating a decode window. A phase locked loop locks a pulse edge of a delayed read data (DRD) signal to an edge of a voltage control oscillator (VCO) clock signal. The edges of the decode window are generated directly from the outer edges of the VCO clock signal. This eliminates errors introduced by quarter cell delay lines, particularly in integrated circuit applications. The transition of the VCO clock signal is used to define a nominal center position coinciding with the mean center position of a data stream. Differential control signals are utilized to shift the VCO transition so that it may be synchronized with the mean bit center position and compensate for non-symmetrical peak jitter. The VCO transition may be shifted without changing the period of the VCO clock signal.
摘要翻译：用于产生解码窗口的方法和装置。锁相环将延迟读数据（DRD）信号的脉冲沿锁定到压控振荡器（VCO）时钟信号的边沿。解码窗口的边缘直接从VCO时钟信号的外沿产生。这消除了四分之一单元延迟线引入的误差，特别是在集成电路应用中。 VCO时钟信号的转换用于定义与数据流的平均中心位置一致的标称中心位置。使用差分控制信号来移位VCO转换，使得其可以与平均位中心位置同步并且补偿非对称峰值抖动。可以在不改变VCO时钟信号的周期的情况下移位VCO转换。

6. 发明授权

US5124669A One-shot circuit for use in a PLL clock recovery circuit 失效
标题翻译：用于PLL时钟恢复电路的单稳态电路
公开(公告)号：US5124669A
公开(公告)日：1992-06-23
申请号：US584351
申请日：1990-09-18
申请人： Michael J. Palmer , Richard G. Yamasaki
发明人： Michael J. Palmer , Richard G. Yamasaki
IPC分类号： H03K3/0232 , H03K3/284 , H03L7/08 , H04L7/033
CPC分类号： H03K3/0232 , H03K3/284 , H03L7/0807 , H04L7/033
摘要： A one-shot whose period is a fraction or multiple of the VCO period in a clock recovery circuit. In a clock recovery circuit using PLL, the one-shot is coupled to the PLL in order to enable/disable the phase detector for cases when the data stream does not consist of uniformly spaced pulses. Without a one-shot, the phase detector in the PLL generates a large error signal whenever a clock pulse occurs without a data pulse. During the times when the phase detector is enabled, a phase comparison is made between the next data edge and the next clock edge. When this comparison is completed, the phase detector is disabled again. In order for the PLL to average out the effects of noise and jitter, the phase detector is enabled one half clock period before the data edge. By doing this, the data edge can shift up to one half clock period. The one-shot of the present invention generates a delayed data signal whose rising edge is used to enable the phase detector, and whose falling edge is compared with the clock edge for disabling the phase detector.
摘要翻译：在时钟恢复电路中，其周期是VCO周期的一部分或多倍的单次触发。在使用PLL的时钟恢复电路中，单触发器耦合到PLL，以便在数据流不由均匀间隔的脉冲组成的情况下启用/禁用相位检测器。没有单次触发，每当时钟脉冲发生而没有数据脉冲时，PLL中的相位检测器产生大的误差信号。在使能相位检测器的时间期间，在下一个数据沿和下一个时钟沿之间进行相位比较。当比较完成时，相位检测器再次被禁止。为了使PLL平滑噪声和抖动的影响，相位检测器在数据沿之前的一个半个时钟周期使能。通过这样做，数据边沿可以移动到一个半个时钟周期。本发明的一个镜头产生延迟的数据信号，其上升沿用于使能相位检测器，并且其下降沿与时钟沿进行比较以禁用相位检测器。

7. 发明授权

US6043944A Method and apparatus for failsafing and extending range for write precompensation 失效
标题翻译：用于写入预补偿的故障切换和扩展范围的方法和装置
公开(公告)号：US6043944A
公开(公告)日：2000-03-28
申请号：US967702
申请日：1997-11-10
申请人： Richard G. Yamasaki , Kiyoshi Fukahori , Tomoaki Ohtsu
发明人： Richard G. Yamasaki , Kiyoshi Fukahori , Tomoaki Ohtsu
IPC分类号： G11B5/09 , G11B20/10
CPC分类号： G11B20/10194
摘要： The present invention prevents catastrophic failures of a write precompensation circuit from occurring without limiting the precompensation range to a small value and also extends the range of precompensation beyond limits imposed by the duty cycle of the clock signal. The present invention prevents catastrophic failure of the write precompensation circuit by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The present invention extends the range of a write precompensation circuit by ORing the clock and the dock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.
摘要翻译：本发明可防止写入预补偿电路的灾难性故障发生，而不将预补偿范围限制在较小的值，并且还将预补偿的范围扩展到由时钟信号的占空比施加的限制之外。本发明通过将比较器的输入或输出与时钟的相反相位进行或运算来防止写入预补偿电路的灾难性故障。 180度延迟时钟强制任何将被遗漏的过渡。本发明通过对延迟时间td的时钟和坞进行OR运算来扩展写入预补偿电路的范围。结果的扩展占空比用于产生较长的预补偿延迟。还提供了一种技术来在宽范围的数据速率下保持恒定的占空比。

8. 发明授权

US5162678A Temperature compensation control circuit for exponential gain function of an AGC amplifier 失效
标题翻译：用于AGC放大器的外部增益功能的温度补偿控制电路
公开(公告)号：US5162678A
公开(公告)日：1992-11-10
申请号：US584201
申请日：1990-09-18
申请人： Richard G. Yamasaki
发明人： Richard G. Yamasaki
IPC分类号： H03F1/30 , H03F3/45 , H03G1/04 , H03G3/10 , H03G3/20
CPC分类号： H03G1/04 , H03F3/45479
摘要： A temperature compensation control circuit to maintain a constant control gain in an AGC (automatic gain control) amplifier. The present invention compensates for the inherent temperature dependence without using any special processing or non-standard device structures. The present invention utilizes the voltage drop across n diodes in series to produce the control voltage difference (V.sub.C -V.sub.C *). These n series diodes are coupled to the collectors of a PNP emitter coupled pair with emitter resistance. This causes the control voltage difference to be dependent on temperature (nkT/q), but this dependency cancels out with the other inherent temperature dependency in the exponential function of the AGC amplifier which is also produced by a diode form. Thus, the present invention provides temperature compensation with minimum component matching problems and without the need for a PTAT (proportional to absolute temperature) current source.
摘要翻译：一种用于在AGC（自动增益控制）放大器中保持恒定控制增益的温度补偿控制电路。本发明补偿固有的温度依赖性，而不使用任何特殊的处理或非标准的器件结构。本发明利用串联的n个二极管上的压降产生控制电压差（VC-VC *）。这些n系列二极管耦合到具有发射极电阻的PNP发射极耦合对的集电极。这导致控制电压差取决于温度（nkT / q），但是这种依赖关系也与由二极管形式产生的AGC放大器的指数函数中的其他固有温度依赖性抵消。因此，本发明提供具有最小组件匹配问题的温度补偿，并且不需要PTAT（与绝对温度成比例）的电流源。

9. 发明授权

US5182477A Bipolar tunable transconductance element 失效
标题翻译：双极可调谐跨导元件
公开(公告)号：US5182477A
公开(公告)日：1993-01-26
申请号：US823067
申请日：1992-01-14
申请人： Richard G. Yamasaki , Geert A. De Veirman
发明人： Richard G. Yamasaki , Geert A. De Veirman
IPC分类号： H03F1/32 , H03F3/45
CPC分类号： H03F3/45071 , H03F1/3211 , H03H11/0422 , H03H11/0433
摘要： The present invention is a new design for transconductance elements useful in high-frequency filters such as fully differential state-variable biquads. The present invention enjoys a large dynamic range. It is built with simple circuitry to reduce parasitic capacitance which impedes high-frequency operation. It is easily tunable for use in programmable filters. It is configured in a fully differential circuit and operates on five volts. The present invention is also very useful for implementing dual-input or multiple input transconductance elements. By incorporating additional current sources in the present invention, another degree of freedom is added to the determination of pole frequency and pole quality factors, when the transconductance is used as a biquad filter building block.
摘要翻译：本发明是用于跨频元件的新设计，其用于高频滤波器，例如全差分状态变量二乘法。本发明具有较大的动态范围。它采用简单的电路构建，以减少阻碍高频操作的寄生电容。它易于调节用于可编程滤波器。它配置在全差分电路中，工作在五伏。本发明对于实现双输入或多输入跨导元件也是非常有用的。通过在本发明中引入额外的电流源，当跨导用作双二阶滤波器构建块时，另外的自由度被添加到极点频率和极点质量因子的确定。

10. 发明授权

US06563655B1 Method and apparatus for failsafing and extending range for write precompensation 失效
标题翻译：用于写入预补偿的故障切换和扩展范围的方法和装置
公开(公告)号：US06563655B1
公开(公告)日：2003-05-13
申请号：US08650850
申请日：1996-05-20
申请人： Richard G. Yamasaki , Tomoaki Ohtsu , Kiyoshi Fukahori
发明人： Richard G. Yamasaki , Tomoaki Ohtsu , Kiyoshi Fukahori
IPC分类号： G11B509
CPC分类号： G11B20/10194
摘要： Catastrophic failures of a write precompensation circuit are prevented from occurring without limiting the precompensation range to a small value and the range of precompensation is extended beyond limits imposed by the duty cycle of the clock signal. Catastrophic failure of the write precompensation circuit is prevented by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The range of a write precompensation circuit is extended by ORing the clock and the clock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.
摘要翻译：可以防止写入预补偿电路发生灾难性故障，而不会将预补偿范围限制在较小的值，并且预补偿的范围延伸到由时钟信号的占空比施加的限制之外。通过将比较器的输入或输出与时钟的相反相位进行或运算来防止写入预补偿电路的灾难性故障。 180度延迟时钟强制任何将被遗漏的过渡。写入预补偿电路的范围通过将时钟和时钟延迟时间td来延长。结果的扩展占空比用于产生较长的预补偿延迟。还提供了一种技术来在宽范围的数据速率下保持恒定的占空比。

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