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    • 2. 发明申请
    • Structure and method for a fast recovery rectifier structure
    • 快速恢复整流器结构的结构和方法
    • US20070145429A1
    • 2007-06-28
    • US11644578
    • 2006-12-22
    • Richard FrancisYang FanEric JohnsonHy Hoang
    • Richard FrancisYang FanEric JohnsonHy Hoang
    • H01L29/80
    • H01L29/872H01L27/0641H01L27/0814H01L27/0817H01L29/0623H01L29/7722H01L29/8083H01L29/861H01L29/8725
    • An apparatus and method for a fast recovery rectifier structure. Specifically, the structure includes a substrate of a first dopant. A first epitaxial layer lightly doped with the first dopant is coupled to the substrate. A first metallization layer is coupled to the first epitaxial layer. A plurality of trenches is recessed into the first epitaxial layer, each of which is coupled to the metallization layer. The device also includes a plurality of wells each doped with a second dopant type, wherein each well is formed beneath and adjacent to a corresponding trench. A plurality of oxide layers is formed on walls and a bottom of a corresponding trench. A plurality of channel regions doped with the first dopant is formed within the first epitaxial layer between two corresponding wells. Each of the plurality of channel regions is more highly doped with the first dopant than the first epitaxial layer.
    • 一种快速恢复整流器结构的装置和方法。 具体地,该结构包括第一掺杂剂的衬底。 轻掺杂有第一掺杂剂的第一外延层耦合到衬底。 第一金属化层耦合到第一外延层。 多个沟槽凹陷到第一外延层中,每个沟槽耦合到金属化层。 该器件还包括多个孔,每个阱均掺杂有第二掺杂剂类型,其中每个阱形成在相应沟槽的下面并与其相邻。 多个氧化物层形成在相应沟槽的壁和底部上。 掺杂有第一掺杂剂的多个沟道区在两个对应的阱之间的第一外延层内形成。 多个沟道区中的每一个与第一外延层比第一掺杂物更加高掺杂。
    • 4. 发明授权
    • Structure and method for a fast recovery rectifier structure
    • 快速恢复整流器结构的结构和方法
    • US07696540B2
    • 2010-04-13
    • US11644578
    • 2006-12-22
    • Richard FrancisYang Yu FanEric JohnsonHy Hoang
    • Richard FrancisYang Yu FanEric JohnsonHy Hoang
    • H01L29/80
    • H01L29/872H01L27/0641H01L27/0814H01L27/0817H01L29/0623H01L29/7722H01L29/8083H01L29/861H01L29/8725
    • An apparatus and method for a fast recovery rectifier structure. Specifically, the structure includes a substrate of a first dopant. A first epitaxial layer lightly doped with the first dopant is coupled to the substrate. A first metallization layer is coupled to the first epitaxial layer. A plurality of trenches is recessed into the first epitaxial layer, each of which is coupled to the metallization layer. The device also includes a plurality of wells each doped with a second dopant type, wherein each well is formed beneath and adjacent to a corresponding trench. A plurality of oxide layers is formed on walls and a bottom of a corresponding trench. A plurality of channel regions doped with the first dopant is formed within the first epitaxial layer between two corresponding wells. Each of the plurality of channel regions is more highly doped with the first dopant than the first epitaxial layer.
    • 一种快速恢复整流器结构的装置和方法。 具体地,该结构包括第一掺杂剂的衬底。 轻掺杂有第一掺杂剂的第一外延层耦合到衬底。 第一金属化层耦合到第一外延层。 多个沟槽凹陷到第一外延层中,每个沟槽耦合到金属化层。 该器件还包括多个孔,每个阱均掺杂有第二掺杂剂类型,其中每个阱形成在相应沟槽的下面并与其相邻。 多个氧化物层形成在相应沟槽的壁和底部上。 掺杂有第一掺杂剂的多个沟道区在两个对应的阱之间的第一外延层内形成。 多个沟道区中的每一个与第一外延层比第一掺杂物更加高掺杂。
    • 6. 发明授权
    • High voltage non punch through IGBT for switch mode power supplies
    • 用于开关电源的高压非穿通IGBT
    • US07534666B2
    • 2009-05-19
    • US11190602
    • 2005-07-27
    • Richard FrancisChiu Ng
    • Richard FrancisChiu Ng
    • H01L21/332
    • H01L29/7395H01L29/0834H01L29/41725H01L29/66333Y10S438/904
    • A process for forming an NPT IGBT in a thin N type silicon wafer in which the bottom surface of a thin silicon wafer (100 microns thick or less) has a shallow reduced lifetime region in its bottom formed by a light species atom implant to a depth of less than about 2.5 microns. A P+ transparent collector region about 0.5 microns deep is formed in the bottom of the damaged region by a boron implant. A collector contact of Al/Ti/NiV and Ag is sputtered onto the collector region and is annealed at 200° C. to 400° C. for 30 to 60 minutes. A pre-anneal step before applying the collector metal can be carried out in vacuum at 300° C. to 400° C. for 30 to 60 seconds.
    • 一种用于在薄N型硅晶片中形成NPT IGBT的工艺,其中薄硅晶片(100微米厚或更小)的底表面在其底部具有浅的减少的寿命区域,其通过光物质原子注入形成深度 小于约2.5微米。 通过硼注入在损伤区域的底部形成约0.5微米深的P +透明集电极区域。 将Al / Ti / NiV和Ag的集电极触点溅射到集电极区域,并在200℃至400℃退火30至60分钟。 在施加集电体金属之前的预退火步骤可以在300℃至400℃的真空中进行30至60秒。