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1. 发明授权

US5761706A Stream buffers for high-performance computer memory system 失效
标题翻译：流缓冲区用于高性能计算机内存系统
公开(公告)号：US5761706A
公开(公告)日：1998-06-02
申请号：US333133
申请日：1994-11-01
申请人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott , Subbarao Palacharla
发明人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott , Subbarao Palacharla
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6022 , G06F2212/6026
摘要： Method and apparatus for a filtered stream buffer coupled to a memory and a processor, and operating to prefetch data from the memory. The filtered stream buffer includes a cache block storage area and a filter controller. The filter controller determines whether a pattern of references has a predetermined relationship, and if so, prefetches stream data into the cache block storage area. Such stream data prefetches are particularly useful in vector processing computers, where once the processor starts to fetch a vector, the addresses of future fetches can be predicted based in the pattern of past fetches. According to various aspects of the present invention, the filtered stream buffer further includes a history table, a validity indicator which is associated with the cache block storage area and indicates which cache blocks, if any, are valid. According to yet another aspect of the present invention, the filtered stream buffer controls random access memory (RAM) chips to stream the plurality of consecutive cache blocks from the RAM into the cache block storage area. According to yet another aspect of the present invention, the stream data includes data for a plurality of strided cache blocks, wherein each of which these strided cache blocks corresponds to an address determined by adding to the first address an integer multiple of the difference between the second address and the first address. According to yet another aspect of the present invention, the processor generates three addresses of data words in the memory, and the filter controller determines whether a predetermined relationship exists among three addresses, and if so, prefetches strided stream data into said cache block storage area.
摘要翻译：耦合到存储器和处理器的经滤波的流缓冲器的方法和装置，并且用于从存储器预取数据。滤波的流缓冲器包括高速缓存块存储区域和过滤器控制器。滤波器控制器确定引用模式是否具有预定关系，如果是，则将流数据预取到高速缓存块存储区域中。这样的流数据预取在向量处理计算机中特别有用，其中一旦处理器开始获取向量，可以基于过去提取的模式来预测未来提取的地址。根据本发明的各个方面，滤波流缓冲器还包括历史表，与高速缓存块存储区相关联的有效性指示符，并指示哪些高速缓存块（如果有的话）是有效的。根据本发明的另一方面，滤波流缓冲器控制随机存取存储器（RAM）芯片以将多个连续高速缓存块从RAM流入高速缓存块存储区域。根据本发明的另一方面，流数据包括用于多个跨度高速缓存块的数据，其中这些跨越高速缓存块中的每一个对应于通过将第一地址相加的确定的地址，第二个地址和第一个地址。根据本发明的另一方面，处理器在存储器中产生数据字的三个地址，并且滤波器控制器确定在三个地址之间是否存在预定的关系，如果是，则将步进流数据预取到所述高速缓存块存储区域。

2. 发明授权

US6029212A Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers 失效
标题翻译：处理任意大小的消息队列的方法，其中消息被写入多个外部寄存器内的对准的外部寄存器的块中
公开(公告)号：US6029212A
公开(公告)日：2000-02-22
申请号：US6449
申请日：1998-01-13
申请人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott , Eric C. Fromm
发明人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott , Eric C. Fromm
IPC分类号： G06F9/30 , G06F9/318 , G06F9/355 , G06F12/02 , G06F13/14 , G06F15/163
CPC分类号： G06F9/342 , G06F12/0292 , G06F9/3004 , G06F9/30101 , G06F9/30134 , G06F9/30138 , G06F9/30167 , G06F9/30189 , G06F9/3861
摘要： A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.
摘要翻译：一种访问具有处理器和与处理器分离的多个存储器位置的系统内的存储器位置的系统和方法。该系统包括通过数据总线连接到处理器的多个外部寄存器，通过数据总线连接到处理器的地址转换装置和地址总线，用于基于写入数据总线的索引来计算连接到多个外部寄存器的传送装置，用于在寻址的存储器位置和外部寄存器之一之间传送数据。

3. 发明授权

US5841973A Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory 失效
标题翻译：在分布式存储器多处理系统中的消息传递，其具有用于原子控制消息存储队列在本地存储器中的尾部指针结构的壳体电路
公开(公告)号：US5841973A
公开(公告)日：1998-11-24
申请号：US615694
申请日：1996-03-13
申请人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott
发明人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott
IPC分类号： G06F15/173 , G06F13/38 , G06F15/16
CPC分类号： G06F15/17381
摘要： A messaging facility in a multiprocessor computer system includes assembly circuitry in a source processing element for assembling a message to be sent from the source processing element to a destination processing element based on information provided from a processor in the source processing element. A network router transmits the assembled message from the source processing element to the destination processing element via an interconnect network. A message queue in a local memory of the destination processing element stores the transmitted message. A control word stored in the local memory of the destination processing element includes a limit field designating a size of the message queue and a tail field designating an index into the corresponding message queue to indicate a location in the message queue where the transmitted message is to be stored. Shell circuitry in the destination processing element atomically reads and updates the tail field.
摘要翻译：多处理器计算机系统中的消息传递设备包括源处理元件中的组装电路，用于根据源处理元件中的处理器提供的信息来组装要从源处理元件发送到目的地处理元件的消息。网络路由器经由互连网络将组合的消息从源处理元件发送到目的地处理元件。目的地处理元件的本地存储器中的消息队列存储发送的消息。存储在目的地处理元件的本地存储器中的控制字包括指定消息队列的大小的限制字段和指定对应消息队列中的索引的尾部字段，以指示消息队列中发送的消息所在的位置存储。目标处理元件中的Shell电路原子地读取和更新尾部字段。

4. 发明授权

US5835925A Using external registers to extend memory reference capabilities of a microprocessor 失效
标题翻译：使用外部寄存器来扩展微处理器的存储器参考能力
公开(公告)号：US5835925A
公开(公告)日：1998-11-10
申请号：US615671
申请日：1996-03-13
申请人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott , Eric C. Fromm
发明人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott , Eric C. Fromm
IPC分类号： G06F9/30 , G06F9/318 , G06F9/355 , G06F12/02 , G06F12/00
CPC分类号： G06F9/342 , G06F12/0292 , G06F9/3004 , G06F9/30101 , G06F9/30134 , G06F9/30138 , G06F9/30167 , G06F9/30189 , G06F9/3861
摘要： A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data bus, address translation means, connected to the processor over the data bus and an address bus, for calculating, based on an index written to the data bus, an address associated with one of the memory locations, and transfer means, connected to the plurality of external registers, for transferring data between the addressed memory location and one of the external registers.
摘要翻译：一种访问具有处理器和与处理器分离的多个存储器位置的系统内的存储器位置的系统和方法。该系统包括通过数据总线连接到处理器的多个外部寄存器，通过数据总线连接到处理器的地址转换装置和地址总线，用于基于写入数据总线的索引来计算连接到多个外部寄存器的传送装置，用于在寻址的存储器位置和外部寄存器之一之间传送数据。

5. 发明授权

US5864738A Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller 失效
标题翻译：使用两条数据路径的大规模并行处理系统：一条将路由器电路连接到互连网络，另一条连接路由器电路连接到I / O控制器
公开(公告)号：US5864738A
公开(公告)日：1999-01-26
申请号：US614859
申请日：1996-03-13
申请人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott
发明人： Richard E. Kessler , Steven M. Oberlin , Steven L. Scott
IPC分类号： G06F12/08 , G06F15/173 , G06F15/80 , G06G13/00
CPC分类号： G06F15/17375 , G06F12/0817 , G06F15/8007
摘要： A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to the interconnect network, the processor and the local memory. Each router circuit includes means for transferring data between the processor and the interconnect network and means for transferring data between the local memory and the interconnect network. An I/O controller is connected to a plurality of the router circuits. Data is then read from the peripheral device and transferred through the I/O controller to local memory of one of the processing elements.
摘要翻译：在具有互连网络和多个处理节点的外围设备和MPP系统之间传送信息的系统和方法。每个处理元件包括处理器，本地存储器和连接到互连网络的路由器电路，处理器和本地存储器。每个路由器电路包括用于在处理器和互连网络之间传送数据的装置和用于在本地存储器和互连网络之间传送数据的装置。 I / O控制器连接到多个路由器电路。然后从外围设备读取数据，并通过I / O控制器传送到其中一个处理元件的本地存储器。

6. 发明授权

US06233704B1 System and method for fault-tolerant transmission of data within a dual ring network 失效
标题翻译：双环网络中数据容错传输的系统和方法
公开(公告)号：US06233704B1
公开(公告)日：2001-05-15
申请号：US08614860
申请日：1996-03-13
申请人： Steven L. Scott , Steven M. Oberlin , Daniel L. Kunkel , Gerald A. Schwoerer
发明人： Steven L. Scott , Steven M. Oberlin , Daniel L. Kunkel , Gerald A. Schwoerer
IPC分类号： G06F1300
CPC分类号： G06F13/426
摘要： A multiple counter-rotating ring computer network system having a permission control scheme for client isolation. The peripheral channel allows two rings to be folded into one longer ring so that faulty nodes can be effectively removed from the network. Or, any of the rings can be masked so that they are unoperational. The network system also allows several client isolation states ranging from complete isolation to master access. These types of isolation allow faulty client devices to be tested while maintaining a high-level of network security by configuring the client to an appropriate isolation state.
摘要翻译：具有用于客户端隔离的许可控制方案的多个反向旋转环计算机网络系统。外围通道允许将两个环折叠成一个较长的环，从而可以有效地从网络上移除故障节点。或者，任何一个戒指都可以被遮蔽，以使它们不可操作。网络系统还允许从完全隔离到主访问的多个客户端隔离状态。这些类型的隔离允许通过将客户端配置为适当的隔离状态来维护高级别的网络安全性来测试故障客户端设备。

7. 发明授权

US06216174B1 System and method for fast barrier synchronization 有权
标题翻译：快速屏障同步的系统和方法
公开(公告)号：US06216174B1
公开(公告)日：2001-04-10
申请号：US09162673
申请日：1998-09-29
申请人： Steven L. Scott , Richard E. Kessler
发明人： Steven L. Scott , Richard E. Kessler
IPC分类号： G06F1580
CPC分类号： G06F9/52 , G06F9/522
摘要： Improved method and apparatus for facilitating fast barrier synchronization in a parallel-processing system. A single input signal and a single output signal, and a single bit of state (“barrier_bit”) is added to each processor to support a barrier. The input and output signal are coupled to a dedicated barrier-logic circuit that includes memory-mapped bit-vector registers to track the “participating” processors and the “joined” processors for the barrier. A “bjoin” instruction executed in a processor causes a pulse to be sent on the output signal, which in turn causes that processor's bit in the dedicated barrier-logic circuit's “joined” register to be set. When the “joined” bits for all participating processors (as indicated by the “participating” register) are all set, the “joined” register is cleared, and a pulse is sent to the input signal of all the participating processors, which in turn causes each of those processor's barrier_bit to be set.
摘要翻译：用于促进并行处理系统中的快速屏障同步的改进的方法和装置。单个输入信号和单个输出信号以及单个位状态（“barrier_bit”）被添加到每个处理器以支持屏障。输入和输出信号耦合到专用的屏障逻辑电路，该电路包括存储器映射的位向量寄存器以跟踪“参与”处理器和用于屏障的“连接”处理器。在处理器中执行的“bjoin”指令使得在输出信号上发送脉冲，这又导致专用势垒逻辑电路的“加入”寄存器中的处理器的位被置位。当所有参与处理器（由“参与”寄存器指示）的“加入”位全部被置位时，“已加入”寄存器被清除，并且脉冲被发送到所有参与处理器的输入信号，反过来导致这些处理器的barrier_bit中的每一个被设置。

8. 发明授权

US08774203B2 One-way message notification with out-of-order packet delivery 有权
标题翻译：单程消息通知，具有无序包传送
公开(公告)号：US08774203B2
公开(公告)日：2014-07-08
申请号：US11759757
申请日：2007-06-07
申请人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
发明人： Steven L. Scott , Dennis C. Abts , Robert Alverson , Edwin Froese
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L49/90 , H04L1/0079 , H04L1/1635 , H04L1/188 , H04L47/10 , H04L47/34
摘要： A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, and to send a message complete packet after all packets in the message are sent. The message complete packet includes an indicator of the number of packets in the message, and the message is recognized as complete in the receiver once the number of packets indicated in the message complete packet have been received for the message. The sender tracks acknowledgment from the receiver of receipt of the sent packets; and notifies the receiver when it has received all packets comprising a part of the message.
摘要翻译：多处理器计算机系统包括发送处理器节点和接收处理器节点。发送处理器节点可操作以将包含消息的一部分的分组发送到接收机，并且在消息中的所有分组被发送之后发送消息完整分组。消息完成分组包括消息中的分组数量的指示符，并且一旦接收到该消息的消息完成分组中指示的分组数量，则该消息在接收机中被识别为完成。发送者跟踪接收到发送的数据包的确认; 并且当它接收到包括消息的一部分的所有分组时通知接收机。

9. 发明授权

US08380935B2 Atomic memory operation cache protocol with opportunistic combining 失效
标题翻译：原子内存操作缓存协议与机会性组合
公开(公告)号：US08380935B2
公开(公告)日：2013-02-19
申请号：US12484165
申请日：2009-06-12
申请人： Dennis C. Abts , Steven L. Scott
发明人： Dennis C. Abts , Steven L. Scott
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F9/526 , G06F12/0815
摘要： An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.
摘要翻译：原子存储器操作高速缓存包括用于缓存原子存储器操作数据的高速缓存存储器，写入定时器和高速缓存控制器。高速缓存控制器可操作以在写定时器期满时，用存储在高速缓存存储器中的一个或多个脏原子存储器操作高速缓存条目来更新主存储器，并且还可操作以用存储的一个或多个脏原子存储器操作高速缓存条目来更新主存储器在从高速缓存存储器中消除一个或多个脏原子存储器操作高速缓存条目之后的缓存存储器中。

10. 发明授权

US08261134B2 Error management watchdog timers in a multiprocessor computer 有权
标题翻译：多处理器计算机中的错误管理看门狗定时器
公开(公告)号：US08261134B2
公开(公告)日：2012-09-04
申请号：US12695491
申请日：2010-01-28
申请人： Dennis C. Abts , Steven L. Scott , Aaron F. Godfrey
发明人： Dennis C. Abts , Steven L. Scott , Aaron F. Godfrey
IPC分类号： G06F11/00 , G11B20/16
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0757 , G06F11/0793 , H04L41/0654 , H04L43/0852
摘要： A multiprocessor computer system comprises one or more watchdog timers operable to detect failure of a memory operation based on passage of a certain timing period from a memory operation being issued without a valid response. An error handler is operable to take corrective action regarding the failed memory operation, such as to provide at least one of hardware state management and application state management.
摘要翻译：多处理器计算机系统包括一个或多个看门狗定时器，其可操作用于基于在没有有效响应的情况下发出的存储器操作的某个定时周期的通过来检测存储器操作的故障。错误处理程序可操作以对故障存储器操作采取纠正措施，例如提供硬件状态管理和应用状态管理中的至少一个。

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