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1. 发明申请

US20070202659A1 FinFET Body Contact Structure 有权
标题翻译： FinFET主体接触结构
公开(公告)号：US20070202659A1
公开(公告)日：2007-08-30
申请号：US11696331
申请日：2007-04-04
申请人： Richard Donze , Karl Erickson , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： H01L21/76
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
摘要翻译：公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。宽鳍片部分和多晶硅多边形形状的顶表面被硅化。通过侧壁间隔物防止硅化物桥接。多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。中心区域与相关联的FinFET的源极和漏极相反地掺杂。

2. 发明申请

US20060091463A1 FinFET body contact structure 有权
标题翻译： FinFET体接触结构
公开(公告)号：US20060091463A1
公开(公告)日：2006-05-04
申请号：US10977768
申请日：2004-10-29
申请人： Richard Donze , Karl Erickson , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
摘要翻译：公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。宽鳍片部分和多晶硅多边形形状的顶表面被硅化。通过侧壁间隔物防止硅化物桥接。多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。中心区域与相关联的FinFET的源极和漏极相反地掺杂。

3. 发明申请

US20060063334A1 Fin FET diode structures and methods for building 审中-公开
标题翻译：翅片FET二极管结构和建筑方法
公开(公告)号：US20060063334A1
公开(公告)日：2006-03-23
申请号：US10944624
申请日：2004-09-17
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff , Laura Zumbrunnen
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff , Laura Zumbrunnen
IPC分类号： H01L21/336
CPC分类号： H01L29/861 , H01L29/785
摘要： FinFET diode structures and methods are provided for building the FinFET diode structures. A FinFET diode structure is created by implanting a diffusion Fin on a first side with a P+ dopant and on a second side with a N+ dopant providing a P+N+ diode structure.
摘要翻译： FinFET二极管结构和方法用于构建FinFET二极管结构。通过在具有P +掺杂剂的第一侧上注入扩散鳍并且在第二侧上用提供P + N +二极管结构的N +掺杂剂注入FinFET二极管结构。

4. 发明申请

US20070072385A1 Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region 失效
公开(公告)号：US20070072385A1
公开(公告)日：2007-03-29
申请号：US11559940
申请日：2006-11-15
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： H01L21/20 , H01L21/00 , H01L21/36
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.

5. 发明申请

US20060060844A1 Electrical open/short contact alignment structure for active region vs. gate region 失效
标题翻译：用于有源区域与栅极区域的电开/短接触对准结构
公开(公告)号：US20060060844A1
公开(公告)日：2006-03-23
申请号：US10944625
申请日：2004-09-17
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.
摘要翻译：公开了一种用于测量多晶硅形状相对于硅区域的对准的装置和方法，其中使用电耦合的存在来确定偏置或未对准的存在。形成多晶硅形状上的桥接顶点。在硅区域上的桥接顶点在这些桥接顶点和硅区域之间产生低电阻连接; ROX（凹陷氧化物）区域上的其他桥接顶点不会在其他桥接顶点和硅区域之间产生低电阻连接。确定哪些桥接顶点具有与硅区域的低电阻连接以及有多少桥接顶点具有与硅区域的低电阻连接，以确定多晶硅形状相对于硅面积的偏置和未对准。

6. 发明申请

US20070102700A1 Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region 失效
标题翻译：有源区域与门极区域的电气开路/短接触对准结构
公开(公告)号：US20070102700A1
公开(公告)日：2007-05-10
申请号：US11559949
申请日：2006-11-15
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.
摘要翻译：公开了一种用于测量多晶硅形状相对于硅区域的对准的装置和方法，其中使用电耦合的存在来确定偏置或未对准的存在。形成多晶硅形状上的桥接顶点。在硅区域上的桥接顶点在这些桥接顶点和硅区域之间产生低电阻连接; ROX（凹陷氧化物）区域上的其他桥接顶点不会在其他桥接顶点和硅区域之间产生低电阻连接。确定哪些桥接顶点具有与硅区域的低电阻连接以及有多少桥接顶点具有与硅区域的低电阻连接，以确定多晶硅形状相对于硅面积的偏置和未对准。

7. 发明申请

US20070068627A1 Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region 失效
公开(公告)号：US20070068627A1
公开(公告)日：2007-03-29
申请号：US11559946
申请日：2006-11-15
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： C23F1/00 , C23C16/00 , H01L21/306
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.

8. 发明申请

US20060136751A1 Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable 有权
公开(公告)号：US20060136751A1
公开(公告)日：2006-06-22
申请号：US11016219
申请日：2004-12-17
申请人： Anthony Bonaccio , Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Anthony Bonaccio , Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G06F12/14
CPC分类号： G06F12/1433 , G06F21/6245
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

9. 发明申请

US20060136858A1 Utilizing fuses to store control parameters for external system components 审中-公开
标题翻译：利用保险丝存储外部系统组件的控制参数
公开(公告)号：US20060136858A1
公开(公告)日：2006-06-22
申请号：US11016214
申请日：2004-12-17
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G11C17/18
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

10. 发明申请

US20060131743A1 Changing chip function based on fuse states 有权
标题翻译：基于保险丝状态改变芯片功能
公开(公告)号：US20060131743A1
公开(公告)日：2006-06-22
申请号：US11016220
申请日：2004-12-17
申请人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
发明人： Karl Erickson , John Fifield , Chandrasekharan Kothandaraman , Phil Paone , William Tonti
IPC分类号： H01L23/48
CPC分类号： G06F21/71
摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
摘要翻译：提供了在设备已经离开制造商的控制之后可以控制电子设备的特定特征的操作和/或访问的技术和系统。可以基于存储在诸如电可编程融合（eFUSES）的非易失性存储元件中的值来提供操作和/或访问。

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