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1. 发明申请

US20060063334A1 Fin FET diode structures and methods for building 审中-公开
标题翻译：翅片FET二极管结构和建筑方法
公开(公告)号：US20060063334A1
公开(公告)日：2006-03-23
申请号：US10944624
申请日：2004-09-17
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff , Laura Zumbrunnen
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff , Laura Zumbrunnen
IPC分类号： H01L21/336
CPC分类号： H01L29/861 , H01L29/785
摘要： FinFET diode structures and methods are provided for building the FinFET diode structures. A FinFET diode structure is created by implanting a diffusion Fin on a first side with a P+ dopant and on a second side with a N+ dopant providing a P+N+ diode structure.
摘要翻译： FinFET二极管结构和方法用于构建FinFET二极管结构。通过在具有P +掺杂剂的第一侧上注入扩散鳍并且在第二侧上用提供P + N +二极管结构的N +掺杂剂注入FinFET二极管结构。

2. 发明申请

US20070072385A1 Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region 失效
公开(公告)号：US20070072385A1
公开(公告)日：2007-03-29
申请号：US11559940
申请日：2006-11-15
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： H01L21/20 , H01L21/00 , H01L21/36
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.

3. 发明申请

US20070102700A1 Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region 失效
标题翻译：有源区域与门极区域的电气开路/短接触对准结构
公开(公告)号：US20070102700A1
公开(公告)日：2007-05-10
申请号：US11559949
申请日：2006-11-15
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.
摘要翻译：公开了一种用于测量多晶硅形状相对于硅区域的对准的装置和方法，其中使用电耦合的存在来确定偏置或未对准的存在。形成多晶硅形状上的桥接顶点。在硅区域上的桥接顶点在这些桥接顶点和硅区域之间产生低电阻连接; ROX（凹陷氧化物）区域上的其他桥接顶点不会在其他桥接顶点和硅区域之间产生低电阻连接。确定哪些桥接顶点具有与硅区域的低电阻连接以及有多少桥接顶点具有与硅区域的低电阻连接，以确定多晶硅形状相对于硅面积的偏置和未对准。

4. 发明申请

US20070068627A1 Electrical Open/Short Contact Alignment Structure for Active Region vs. Gate Region 失效
公开(公告)号：US20070068627A1
公开(公告)日：2007-03-29
申请号：US11559946
申请日：2006-11-15
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： C23F1/00 , C23C16/00 , H01L21/306
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.

5. 发明申请

US20060091463A1 FinFET body contact structure 有权
标题翻译： FinFET体接触结构
公开(公告)号：US20060091463A1
公开(公告)日：2006-05-04
申请号：US10977768
申请日：2004-10-29
申请人： Richard Donze , Karl Erickson , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
摘要翻译：公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。宽鳍片部分和多晶硅多边形形状的顶表面被硅化。通过侧壁间隔物防止硅化物桥接。多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。中心区域与相关联的FinFET的源极和漏极相反地掺杂。

6. 发明申请

US20070202659A1 FinFET Body Contact Structure 有权
标题翻译： FinFET主体接触结构
公开(公告)号：US20070202659A1
公开(公告)日：2007-08-30
申请号：US11696331
申请日：2007-04-04
申请人： Richard Donze , Karl Erickson , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： H01L21/76
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66795
摘要： A FinFET body contact structure and a method for creating the FinFET body contact structure are disclosed. The body contact structure comprises a wide fin portion of a semiconductor fin, the wide fin portion having a polysilicon polygon shape formed on a top surface of the wide fin portion. The polysilicon polygon shape has a center area having no polysilicon. FinFETs are formed on two vertical surfaces of the wide fin portion and gates of the FinFETs are coupled to the polysilicon polygon shape. Top surfaces of the wide fin portion and the polysilicon polygon shape are silicided. Silicide bridging is prevented by sidewall spacers. All convex angles on the polysilicon polygon shape are obtuse enough to prevent creation of bridging vertices. The center area is doped of an opposite type from a source and a drain of an associated FinFET.
摘要翻译：公开了FinFET体接触结构和用于产生FinFET体接触结构的方法。本体接触结构包括半导体鳍片的宽鳍片部分，宽鳍片部分形成在宽鳍片部分的顶表面上的多晶硅多边形形状。多晶硅多晶形状具有不具有多晶硅的中心区域。 FinFET形成在宽鳍片部分的两个垂直表面上，并且FinFET的栅极耦合到多晶硅多边形形状。宽鳍片部分和多晶硅多边形形状的顶表面被硅化。通过侧壁间隔物防止硅化物桥接。多晶硅多边形形状上的所有凸角都足够钝，以防止桥接顶点的产生。中心区域与相关联的FinFET的源极和漏极相反地掺杂。

7. 发明申请

US20060060844A1 Electrical open/short contact alignment structure for active region vs. gate region 失效
标题翻译：用于有源区域与栅极区域的电开/短接触对准结构
公开(公告)号：US20060060844A1
公开(公告)日：2006-03-23
申请号：US10944625
申请日：2004-09-17
申请人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
发明人： Richard Donze , Karl Erickson , William Hovis , John Sheets , Jon Tetzloff
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34 , H01L29/785
摘要： An apparatus and method are disclosed for measuring alignment of polysilicon shapes relative to a silicon area wherein the presence of an electrical coupling is used to determine the presence of bias or misalignment. Bridging vertices on the polysilicon shapes are formed. Bridging vertices over the silicon area create low resistance connections between those bridging vertices and the silicon area; other bridging vertices over ROX (recessed oxide) areas do not create low resistance connections between those other bridging vertices and the silicon area. Determining which bridging vertices have low resistance connections to the silicon area and how many bridging vertices have low resistance connections to the silicon area are used to determine the bias and misalignment of the polysilicon shapes relative to the silicon area.
摘要翻译：公开了一种用于测量多晶硅形状相对于硅区域的对准的装置和方法，其中使用电耦合的存在来确定偏置或未对准的存在。形成多晶硅形状上的桥接顶点。在硅区域上的桥接顶点在这些桥接顶点和硅区域之间产生低电阻连接; ROX（凹陷氧化物）区域上的其他桥接顶点不会在其他桥接顶点和硅区域之间产生低电阻连接。确定哪些桥接顶点具有与硅区域的低电阻连接以及有多少桥接顶点具有与硅区域的低电阻连接，以确定多晶硅形状相对于硅面积的偏置和未对准。

8. 发明申请

US20070128740A1 Polysilicon Conductor Width Measurement for 3-Dimensional FETs 审中-公开
标题翻译：三维FET的多晶硅导体宽度测量
公开(公告)号：US20070128740A1
公开(公告)日：2007-06-07
申请号：US11670008
申请日：2007-02-01
申请人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： H01L21/66
CPC分类号： H01L27/1203 , H01L22/34 , H01L29/785
摘要： An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
摘要翻译：公开了一种用于确定三维场效应晶体管（FinFET）的多晶硅导体宽度的装置和方法。使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。第一电阻器具有第一线宽度。第二电阻具有第二线宽。第二行宽度与第一行宽度略有不同。有利地，第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。复合测试结构不仅允许计算多晶硅导体宽度，而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。

9. 发明申请

US20060063317A1 Polysilicon conductor width measurement for 3-dimensional FETs 失效
标题翻译：三维FET的多晶硅导体宽度测量
公开(公告)号：US20060063317A1
公开(公告)日：2006-03-23
申请号：US10944622
申请日：2004-09-17
申请人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： H01L21/338
CPC分类号： H01L27/1203 , H01L22/34 , H01L29/785
摘要： An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
摘要翻译：公开了一种用于确定三维场效应晶体管（FinFET）的多晶硅导体宽度的装置和方法。使用其中在多个硅“鳍”上形成多晶硅导体的拓扑构造两个或更多个电阻器。第一电阻器具有第一线宽度。第二电阻具有第二线宽。第二行宽度与第一行宽度略有不同。有利地，第一线宽度等于在特定半导体技术中用于制造FET栅极的标称设计宽度。电阻的电阻测量和使用电阻测量的随后的计算用于确定由半导体工艺产生的实际多晶硅导体宽度。复合测试结构不仅允许计算多晶硅导体宽度，而且提供了在计算中使用的宽度差不会引起多晶硅导体的不良刻蚀特性的证据。

10. 发明申请

US20050201188A1 Method and apparatus for improving performance margin in logic paths 失效
标题翻译：提高逻辑路径性能余量的方法和装置
公开(公告)号：US20050201188A1
公开(公告)日：2005-09-15
申请号：US10798911
申请日：2004-03-11
申请人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
发明人： Richard Donze , William Hovis , Terrance Kueper , John Sheets , Jon Tetzloff
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , G06F1/206 , G06F1/26 , G11C7/04 , G11C11/4074
摘要： An apparatus and method is disclosed for improving timing margins of logic paths on a semiconductor chip. Typical logic embodiments, such as CMOS (Complementary Metal Oxide Semiconductor), have path delays that become shorter as supply voltage is increased. Embodiments of the present invention store product data on each particular chip. The product data includes, for examples, but not limited to, a voltage range having a low limit voltage and a high limit voltage, a limit temperature, and performance of the particular chip in storage for the particular chip. Each chip has a voltage controller, a timer, and a thermal monitor. The voltage controller communicates with a voltage regulator and dynamically causes a voltage supply coupled to the chip to be as high as possible in the voltage range, subject to the limit temperature.
摘要翻译：公开了一种用于改善半导体芯片上的逻辑路径的时序余量的装置和方法。诸如CMOS（互补金属氧化物半导体）的典型逻辑实施例具有随着电源电压增加而变短的路径延迟。本发明的实施例将产品数据存储在每个特定芯片上。产品数据包括例如但不限于具有用于特定芯片的存储器中的特定芯片的低限电压和上限电压，极限温度和性能的电压范围。每个芯片都有一个电压控制器，一个定时器和一个热量监视器。电压控制器与电压调节器通信，动态地使耦合到芯片的电压在电压范围内尽可能高，受限于极限温度。

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