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1. 发明授权

US06175319B1 Power-tailored write-current method 失效
标题翻译：电源定制写入电流方式
公开(公告)号：US06175319B1
公开(公告)日：2001-01-16
申请号：US09315565
申请日：1999-05-20
申请人： Richard Crane Schneider , Keith Gary Boyer , Norman Lee Koren
发明人： Richard Crane Schneider , Keith Gary Boyer , Norman Lee Koren
IPC分类号： H03M506
CPC分类号： H03M5/06 , G11B20/10009
摘要： A method of generating an encoded signal from a sequential stream of digital data, where the encoded signal has a non-power carrying null state and a power carrying active state with two opposing polarities. Logical one bits are distinguished from logical zero bits by inverting the encoded signal's polarity at the start of only the logical one bits. The encoded signal is set to the active state during a bit set-up period before, and held in the active state during a bit hold period after each polarity inversion. At other times the encoded signal is set to the null state. The method may include the addition of equalization pulses during strings of consecutive logical zero bits to keep the encoded signal from remaining in the null state for extended periods. Each equalization pulse may be preceded by an equalization set-up period and followed by an equalization hold period where the encoded signal is in the active state. In the preferred embodiment the set-up periods, hold periods, and equalization pulse periods are one-third the duration period of the logical bits.
摘要翻译：一种从数字数据的顺序流生成编码信号的方法，其中编码信号具有非运行无效状态和具有两个相反极性的功率传送活动状态。逻辑1比特与逻辑0比特不同，仅在逻辑1比特的起始处反转编码信号的极性。编码信号在比特建立周期之前被设置为有效状态，并且在每个极性反转之后的比特保持期间保持在活动状态。在其他时间，编码信号被设置为零状态。该方法可以包括在连续的逻辑零比特串期间添加均衡脉冲以保持编码的信号在长时间内保持在空状态。每个均衡脉冲之前可以是均衡建立周期，随后是均衡保持周期，其中编码信号处于活动状态。在优选实施例中，建立周期，保持周期和均衡脉冲周期是逻辑比特的持续时间周期的三分之一。

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