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1. 发明授权

US06175319B1 Power-tailored write-current method 失效
标题翻译：电源定制写入电流方式
公开(公告)号：US06175319B1
公开(公告)日：2001-01-16
申请号：US09315565
申请日：1999-05-20
申请人： Richard Crane Schneider , Keith Gary Boyer , Norman Lee Koren
发明人： Richard Crane Schneider , Keith Gary Boyer , Norman Lee Koren
IPC分类号： H03M506
CPC分类号： H03M5/06 , G11B20/10009
摘要： A method of generating an encoded signal from a sequential stream of digital data, where the encoded signal has a non-power carrying null state and a power carrying active state with two opposing polarities. Logical one bits are distinguished from logical zero bits by inverting the encoded signal's polarity at the start of only the logical one bits. The encoded signal is set to the active state during a bit set-up period before, and held in the active state during a bit hold period after each polarity inversion. At other times the encoded signal is set to the null state. The method may include the addition of equalization pulses during strings of consecutive logical zero bits to keep the encoded signal from remaining in the null state for extended periods. Each equalization pulse may be preceded by an equalization set-up period and followed by an equalization hold period where the encoded signal is in the active state. In the preferred embodiment the set-up periods, hold periods, and equalization pulse periods are one-third the duration period of the logical bits.
摘要翻译：一种从数字数据的顺序流生成编码信号的方法，其中编码信号具有非运行无效状态和具有两个相反极性的功率传送活动状态。逻辑1比特与逻辑0比特不同，仅在逻辑1比特的起始处反转编码信号的极性。编码信号在比特建立周期之前被设置为有效状态，并且在每个极性反转之后的比特保持期间保持在活动状态。在其他时间，编码信号被设置为零状态。该方法可以包括在连续的逻辑零比特串期间添加均衡脉冲以保持编码的信号在长时间内保持在空状态。每个均衡脉冲之前可以是均衡建立周期，随后是均衡保持周期，其中编码信号处于活动状态。在优选实施例中，建立周期，保持周期和均衡脉冲周期是逻辑比特的持续时间周期的三分之一。

2. 发明授权

US5754593A Write equalization for partial response channels 失效
标题翻译：部分响应通道的写均衡
公开(公告)号：US5754593A
公开(公告)日：1998-05-19
申请号：US564698
申请日：1995-11-29
申请人： Norman Lee Koren
发明人： Norman Lee Koren
IPC分类号： G11B20/14 , G11B20/10 , H03M7/14 , H04L25/08 , H04L25/497 , H04L5/12
CPC分类号： G11B20/10009
摘要： A method of write equalization in digital data recording systems comprising the steps of: providing a digital data signal to be recorded on recordable media, wherein the digital data signal includes 1s and 0s spaced at time interval T with 1s represented by a signal transition between first and second signal levels and 0s represented by no signal transition, and in which there is a minimum of d+1 intervals T between transitions; providing write equalization pulses of width WT for each 0 starting with the (d+1)th 0 following a 1; and causing a transition of a write equalization pulse adjacent to a 1 to occupy the same position as the transition of the 1 so that there is no transition for the 1. In one embodiment, the initial transition of the first added 0 pulse following a 1 is advanced in time so that it occupies the same position as the transition for the 1. In a second embodiment, the second transition of the last added 0 pulse preceding a 1 is delayed in time so that it occupies the same transition as the transition for the 1.
摘要翻译：一种数字数据记录系统中的写入均衡的方法，包括以下步骤：提供待记录在可记录介质上的数字数据信号，其中数字数据信号包括以时间间隔T隔开的1和0，和无信号转换表示的第二信号电平和0，并且其中转换之间存在最小的d + 1间隔T. 提供每个0的宽度WT的写入均衡脉冲，从1之后的（d + 1）0开始; 并且使得与1相邻的写入均衡脉冲的转变占据与1的转变相同的位置，使得对于1不存在转变。在一个实施例中，第一个添加的0个脉冲的初始转变遵循1 在时间上是先进的，使得它占据与1的转变相同的位置。在第二实施例中，在1之前的最后添加的0个脉冲的第二个转换被延迟，使得它处于与 1。

3. 发明授权

US5742244A Nonlinear run-length coding 失效
标题翻译：非线性游程编码
公开(公告)号：US5742244A
公开(公告)日：1998-04-21
申请号：US636075
申请日：1996-04-22
申请人： Robert Earl Swanson , Thomas Daniel Carr , Norman Lee Koren
发明人： Robert Earl Swanson , Thomas Daniel Carr , Norman Lee Koren
IPC分类号： G11B20/14 , H03M5/14 , H03M7/00
CPC分类号： G11B20/1426 , H03M5/145
摘要： An input string of binary data bits which is a random sequence of 0s and 1s is selectively spaced encoded into an output string of binary channel bits which is a sequence of 0s and 1s. An input string of binary data bits are recursively encoded according to run-length selection means having rate p/q where p is the number of input data bits that are encoded into q-channel bits. The channel bits obey constraints such that the encoding specifies an ordered n element list of integers that are the lengths of the selected runs of consecutive zeros, denoted b.sub.0 -1, b.sub.1 -1, . . . , b.sub.n-1 -1, and such that the element list of integers does not contain all the integers between the minimum element, b.sub.0, and the maximum element, b.sub.n-1.
摘要翻译：作为0s和1s的随机序列的二进制数据位的输入串被选择性地间隔编码为作为0和1的序列的二进制通道位的输出串。根据具有速率p / q的游程长度选择装置对二进制数据比特的输入串进行递归编码，其中p是编码为q信道比特的输入数据比特数。信道位服从约束，使得编码指定作为所选择的连续零运行的长度的整数的有序n个元素列表，表示为b0-1，b1-1，。。。，bn-1-1，并且使得整数的元素列表不包含最小元素b0和最大元素bn-1之间的所有整数。

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