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1. 发明授权

US06952113B2 Method of reducing leakage current in sub one volt SOI circuits 有权
标题翻译：降低亚一伏SOI电路漏电流的方法
公开(公告)号：US06952113B2
公开(公告)日：2005-10-04
申请号：US10644211
申请日：2003-08-20
申请人： Richard B. Brown , Ching-Te K. Chuang , Peter W. Cook , Koushik K. Das , Rajiv V. Joshi
发明人： Richard B. Brown , Ching-Te K. Chuang , Peter W. Cook , Koushik K. Das , Rajiv V. Joshi
IPC分类号： H03K19/00 , A03K19/003
CPC分类号： H03K19/0016
摘要： A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETs) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.
摘要翻译：具有降低的亚阈值泄漏的多阈值集成电路（IC）和减少泄漏的方法。电路逻辑电路和电源连接（V SUB）和GND之间的可选供电开关器件（NFET和/或PFET）的电路具有比正常电路器件更高的阈值。当供电开关装置打开时，一些装置可能具有降低的阈值。具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。或者，可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。中间电源连接在器件上可能具有去耦电容，器件可以锥形化，以获得最佳堆叠高度和最佳锥度比，以最大限度地减少电路泄漏和电路延迟。

2. 发明授权

US07956669B2 High-density low-power data retention power gating with double-gate devices 有权
标题翻译：具有双栅极器件的高密度低功耗数据保持功率门控
公开(公告)号：US07956669B2
公开(公告)日：2011-06-07
申请号：US11106913
申请日：2005-04-15
申请人： Ching-Te K. Chuang , Koushik K. Das , Keunwoo Kim
发明人： Ching-Te K. Chuang , Koushik K. Das , Keunwoo Kim
IPC分类号： H03K17/687
CPC分类号： H01L27/105 , G11C5/14 , H01L27/11 , H01L27/1116 , H01L29/785 , H01L29/78648 , H03K3/356156
摘要： A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.
摘要翻译：具有强大数据保持能力的新型电源门控结构，仅使用一个单栅极器件来提供电源门控开关和虚拟电源/接地二极管钳位功能。该方案降低了电源门控结构的晶体管数量，面积和电容，从而提高了电路性能，功率和泄漏。该方案通过基于混合模式物理的二维数值模拟与常规电力门控结构进行比较。还提出了拟议方案的虚拟供应/地面反弹分析。

3. 发明授权

US07085798B2 Sense-amp based adder with source follower pass gate evaluation tree 失效
公开(公告)号：US07085798B2
公开(公告)日：2006-08-01
申请号：US10167276
申请日：2002-06-10
申请人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
发明人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
IPC分类号： G06F7/50
CPC分类号： G06F7/508
摘要： A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

4. 发明授权

US06789099B2 Sense-amp based adder with source follower evaluation tree 有权
公开(公告)号：US06789099B2
公开(公告)日：2004-09-07
申请号：US10167170
申请日：2002-06-10
申请人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
发明人： Jae-Joon Kim , Ching-Te K. Chuang , Rajiv V. Joshi , Kaushik Roy
IPC分类号： G06F750
CPC分类号： G06F7/508 , G06F7/503 , G06F7/507 , G06F2207/3872 , G06F2207/4814
摘要： A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

5. 发明授权

US06798682B2 Reduced integrated circuit chip leakage and method of reducing leakage 有权
标题翻译：降低集成电路芯片泄漏和减少泄漏的方法
公开(公告)号：US06798682B2
公开(公告)日：2004-09-28
申请号：US10307168
申请日：2002-11-29
申请人： Ching-Te K. Chuang , Rajiv V. Joshi , Michael G. Rosenfield
发明人： Ching-Te K. Chuang , Rajiv V. Joshi , Michael G. Rosenfield
IPC分类号： G11C11413
CPC分类号： G11C11/412
摘要： An integrated circuit that may include an array such as a static random access memory (SRAM) with high threshold device array devices and in selected other devices to reduce leakage. Devices with high threshold have a thicker gate oxide or a high k dielectric gate oxide that is selected based on threshold voltage (VT) variations with gate oxide dielectric type or gate oxide thickness for the particular technology, e.g., PD SOI CMOS. High threshold devices may be used in non-core circuits, e.g., test circuits. Also, non-critical paths may be identified and a non-critical path margin identified. A thicker device threshold is selected for non-critcal path FETs based on the non-critical path margin. Non-critical path delays are re-checked. FETs are formed with the selected thicker gate oxide for any non-critical paths passing the re-check and in array FETs with non-selected FETs being formed with normal gate oxide thickness.
摘要翻译：可以包括阵列的集成电路，例如具有高阈值器件阵列器件的静态随机存取存储器（SRAM）和选定的其它器件以减少泄漏。具有高阈值的器件具有较厚的栅极氧化物或高k电介质栅极氧化物，其基于用于特定技术（例如PD SOI CMOS）的栅极氧化物介电类型或栅极氧化物厚度的阈值电压（VT）变化来选择。高阈值器件可用于非核心电路，例如测试电路。此外，可以识别非关键路径并且识别非关键路径余量。基于非关键路径裕度为非临界路径FET选择较厚的器件阈值。重新检查非关键路径延迟。对于通过重新检查的任何非关键路径和在具有正常栅极氧化物厚度的非选择FET形成的阵列FET中形成FET。

6. 发明授权

US08086917B2 Methods for characterizing device variation in electronic memory circuits 有权
标题翻译：表征电子存储器电路中器件变化的方法
公开(公告)号：US08086917B2
公开(公告)日：2011-12-27
申请号：US12542187
申请日：2009-08-17
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/5002
摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.
摘要翻译：电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变电压差＆Dgr ;在它们的栅 - 源电压之间，和（ii）改变＆Dgr; 直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

7. 发明申请

US20090091346A1 CIRCUITS AND METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS 有权
标题翻译：用于表征电子存储器电路中设备变化的电路和方法
公开(公告)号：US20090091346A1
公开(公告)日：2009-04-09
申请号：US11866502
申请日：2007-10-03
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Saibal Mukhopadhyay
IPC分类号： G01R31/26
CPC分类号： G11C29/50 , G11C11/41 , G11C29/12005 , G11C2029/5002
摘要： A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level.
摘要翻译：电路包括比较器电路，其被配置为使得当其第一和第二输入在第一状态和第二输入之间转变时，其输出从第一数字逻辑电平切换到第二数字逻辑电平，其中第一输入具有大于施加电压的施加电压第二输入和第二状态，其中第一输入具有小于第二输入处的施加电压的施加电压。多个单元各自具有在场效应晶体管之间的输出节点处互连的至少一个串联连接的场效应晶体管。解码逻辑被配置为选择用于测量的给定的一个单元，并且将所述单元中的给定单元的输出节点选择性地互连到比较器电路的第一输入。电压供应电路被配置为（i）向被选择用于测量的给定一个单元的一对晶体管的栅极施加电压，使得该对晶体管在线性区域中工作，并且具有可变的电压差在其栅极至源极电压之间，和（ii）改变增量，直到比较器电路输出从第一数字逻辑电平切换到第二数字逻辑电平。

8. 发明授权

US07642864B2 Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect 有权
标题翻译：影响NBTI（负偏压温度不稳定）效应和/或PBTI（正偏温度不稳定）效应的电路和设计结构
公开(公告)号：US07642864B2
公开(公告)日：2010-01-05
申请号：US12021459
申请日：2008-01-29
申请人： Ching-Te K. Chuang , Jae-Joon Kim , Tae-Hyoung Kim , Pong-Fei Lu , Saibal Mukhopadhyay , Rahul M. Rao , Shao-yi Wang
发明人： Ching-Te K. Chuang , Jae-Joon Kim , Tae-Hyoung Kim , Pong-Fei Lu , Saibal Mukhopadhyay , Rahul M. Rao , Shao-yi Wang
IPC分类号： G01R23/00 , G01R27/00 , G01R27/28 , H03B5/24 , H03K3/03
CPC分类号： H03K3/0315
摘要： A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates.
摘要翻译：环形振荡器具有大于或等于3的奇数NOR门，每个具有第一和第二输入端子，电压源端子和输出端子。所有NOR门的第一输入端互连，每个NOR门的输出端连接到紧邻的一个NOR门的第二输入端。在应力模式期间，电压供应和控制块向互连的第一输入端施加应力使能信号，并向电压端提供增加的电源电压。在测量模式期间，该模块接地互连的第一输入端，并向电源端施加正常的电源电压。还包括类似的基于NAND门的电路，组合NAND和NOR方面的电路，电路与环形振荡器，其中逆变器可以直接耦合或通过反向路径耦合，以及用于测量偏置温度不稳定性效应的电路通过门。

9. 发明申请

US20090302354A1 High Density Stable Static Random Access Memory 有权
标题翻译：高密度稳定静态随机存取存储器
公开(公告)号：US20090302354A1
公开(公告)日：2009-12-10
申请号：US11865780
申请日：2007-10-02
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jante Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jante Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer
摘要翻译：存储电路包括多个位线结构，多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。每个单元在对应的一个字线结构的控制下选择性地耦合到位线结构中的相应一个，并且每个单元又包括具有至少第一n型场效应的逻辑存储元件晶体管和至少第一p型场效应晶体管。所述至少第一n型场效应晶体管形成有尺寸适于减小位线结构的电容的相对较厚的掩埋氧化物层，并且所述至少第一p型场效应晶体管形成有相对较薄的掩埋氧化物层

10. 发明授权

US08526219B2 Enhanced static random access memory stability using asymmetric access transistors and design structure for same 失效
标题翻译：增强的静态随机存取存储稳定性采用非对称存取晶体管和设计结构相同
公开(公告)号：US08526219B2
公开(公告)日：2013-09-03
申请号：US13367495
申请日：2012-02-07
申请人： Aditya Bansal , Ching-Te K. Chuang , Jae-Joon Kim , Shih-Hsien Lo , Rahul M. Rao
发明人： Aditya Bansal , Ching-Te K. Chuang , Jae-Joon Kim , Shih-Hsien Lo , Rahul M. Rao
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein.
摘要翻译：存储电路包括多个位线结构（每个都包括真和互补位线），多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。每个单元包括逻辑存储元件，选择性地将给定的一个真位线耦合到逻辑存储元件的第一存取晶体管和选择性地将对应的给定的一个互补位线耦合到逻辑存储器的第二存取晶体管元件。第一和第二存取晶体管中的一个或两个被配置为具有不对称电流特性，以实现READ和WRITE边缘的独立增强。还包括在6-T范围内的是包括在机器可读介质中的一个或多个设计结构，包括如本文所述的电路。

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