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1. 发明授权

US06623161B2 Method and apparatus for identifying and correcting line artifacts in a solid state X-ray detector 有权
标题翻译：用于识别和校正固态X射线检测器中的线假象的方法和装置
公开(公告)号：US06623161B2
公开(公告)日：2003-09-23
申请号：US09682386
申请日：2001-08-28
申请人： Richard Aufrichtig , Paul R. Granfors , Douglas Albagli , George E. Possin , John M. Boudry
发明人： Richard Aufrichtig , Paul R. Granfors , Douglas Albagli , George E. Possin , John M. Boudry
IPC分类号： G01D1800
CPC分类号： G01N23/04 , A61B6/5258
摘要： A method is provided for identifying detector elements in a solid state X-ray detector susceptible to causing line artifacts due to faulty detector elements that leak charge. A portion of the X-ray detector is covered by a radiation occluding material and the detector is exposed to a level of radiation sufficient to reach a predetermined threshold in the exposed portion of the detector. An image representative of the radiation is acquired and further analyzed to determine whether line artifacts exist. Data lines found to exhibit line artifacts are stored in the image processor.
摘要翻译：提供了一种用于识别固体X射线检测器中的检测器元件的方法，其易于由于泄漏电荷的检测器元件故障而导致线路伪影。 X射线检测器的一部分由辐射阻塞材料覆盖，并且检测器暴露于足以在检测器的暴露部分中达到预定阈值的辐射水平。获取代表辐射的图像并进一步分析以确定是否存在线条伪影。被发现呈现线条伪影的数据线被存储在图像处理器中。

2. 发明授权

US5920070A Solid state area x-ray detector with adjustable bias 失效
标题翻译：具有可调偏置的固态区X射线检测器
公开(公告)号：US5920070A
公开(公告)日：1999-07-06
申请号：US758604
申请日：1996-11-27
申请人： Scott W. Petrick , Larry R. Skrenes , Paul R. Granfors , George E. Possin
发明人： Scott W. Petrick , Larry R. Skrenes , Paul R. Granfors , George E. Possin
IPC分类号： G01T1/20 , G01T1/24 , H01L27/14 , H01L31/09 , H04N5/325
CPC分类号： G01T1/24 , H04N5/325
摘要： A large area solid state x-ray detector employs a number of photodiodes that are charged electrically then discharged by exposure to x-ray. Ghost images resulting from release of charge trapped in photodiodes during prior exposures are eliminated by adjusting the biasing during a reset portion of the imaging cycle. Biasing may be increased to decrease the recharge time or reversed in polarity to evenly discharge the diodes or decreased to preserve the offset so that it may be removed from subsequent images by image processing.
摘要翻译：大面积的固态X射线检测器采用许多光电二极管，其电充电然后通过暴露于X射线放电。通过在成像周期的复位部分期间调整偏压来消除在先前曝光期间由于释放被俘获在光电二极管中的电荷而产生的鬼图像。可以增加偏置以减少再充电时间或极性反转以均匀地放电二极管或减小以保持偏移，使得其可以通过图像处理从后续图像中去除。

3. 发明授权

US5616524A Repair method for low noise metal lines in thin film imager devices 失效
标题翻译：薄膜成像设备中低噪声金属线路的修复方法
公开(公告)号：US5616524A
公开(公告)日：1997-04-01
申请号：US580094
申请日：1995-12-22
申请人： Ching Y. Wei , Jianqiang Liu , Roger S. Salisbury , Robert F. Kwasnick , George E. Possin , Douglas Albagli
发明人： Ching Y. Wei , Jianqiang Liu , Roger S. Salisbury , Robert F. Kwasnick , George E. Possin , Douglas Albagli
IPC分类号： H01L21/66 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L27/146 , H01L21/465
CPC分类号： H01L21/76892 , Y10T29/49162
摘要： A method of repairing an open circuit defect in a damaged address line in a thin film electronic imager device includes the steps of forming a repair area on the device so as to expose the open-circuit defect in the damaged address line and then depositing a conductive material to form a second conductive component and to coincidentally form a repair shunt in the repair area so as to electrically bridge the defect. The step of forming the repair area includes the steps of ablating dielectric material disposed over the first conductive component in the repair area, and etching the repair area so as to remove dielectric material disposed over the defect in the address line in the repair area such that the surface of the address line conductive material is exposed but is not contaminated by the removal of the overlying dielectric material. A layer of photoresist is deposited over the imager device prior to forming the repair area, such that the photoresist layer is patterned during the ablating step and serves as a mask during the etch step.
摘要翻译：在薄膜电子成像装置中修复损坏的地址线中的开路缺陷的方法包括以下步骤：在设备上形成修复区域，以暴露损坏的地址线中的开路缺陷，然后沉积导电材料以形成第二导电部件并且在修复区域中巧合地形成修复分路，从而电连接缺陷。形成修复区域的步骤包括以下步骤：消除设置在修复区域中的第一导电部件上的介电材料，并蚀刻修复区域，以便去除在修复区域中的地址线上的缺陷上的介电材料，使得地址线导电材料的表面被暴露，但不会被除去上覆电介质材料污染。在形成修复区域之前，在成像器装置上沉积一层光致抗蚀剂，使得光刻胶层在烧蚀步骤期间被图案化，并在蚀刻步骤期间用作掩模。

4. 发明授权

US5273920A Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface 失效
标题翻译：利用栅极电介质/半导体层界面的氢等离子体处理制造薄膜晶体管的方法
公开(公告)号：US5273920A
公开(公告)日：1993-12-28
申请号：US939746
申请日：1992-09-02
申请人： Robert F. Kwasnick , George E. Possin
发明人： Robert F. Kwasnick , George E. Possin
IPC分类号： H01L21/30 , H01L29/786 , H01L21/265
CPC分类号： H01L29/4908 , H01L21/3003 , H01L29/66765 , H01L29/78669 , Y10S438/91
摘要： A method of fabricating a thin film transistor (TFT) includes the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer of silicon nitride over the gate conductor; treating the exposed silicon nitride on the surface of the gate dielectric layer with a hydrogen plasma at a power level of at least 44 mW/cm.sup.2 for at least 5 minutes; depositing a layer of amorphous silicon semiconductor material over the gate dielectric layer; depositing a layer of n+ doped silicon over the treated amorphous silicon surface; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The deposition of the TFT material layers and the hydrogen plasma treatment is preferably by plasma enhanced chemical vapor deposition.
摘要翻译：制造薄膜晶体管（TFT）的方法包括在基板上形成栅极导体的步骤; 在栅极导体上沉积氮化硅栅极电介质层; 用至少44mW / cm 2的功率水平的氢等离子体处理所述栅极电介质层的表面上暴露的氮化硅至少5分钟; 在所述栅极电介质层上沉积非晶硅半导体材料层; 在所处理的非晶硅表面上沉积n +掺杂硅层; 在n +掺杂层上沉积一层源极/漏极金属化层; 以及图案化源极/漏极金属化层和下层n +掺杂层的部分以形成源极和漏极。 TFT材料层的沉积和氢等离子体处理优选通过等离子体增强化学气相沉积。

5. 发明授权

US5241192A Fabrication method for a self-aligned thin film transistor having reduced end leakage and device formed thereby 失效
标题翻译：具有减小的端部泄漏的自对准薄膜晶体管的制造方法以及由此形成的器件
公开(公告)号：US5241192A
公开(公告)日：1993-08-31
申请号：US862125
申请日：1992-04-02
申请人： George E. Possin , Ching-Yeu Wei
发明人： George E. Possin , Ching-Yeu Wei
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/786
CPC分类号： H01L29/78696 , H01L27/1214 , H01L29/66765 , Y10S438/978
摘要： The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.
摘要翻译：根据本发明形成的TFT结构包括TFT体，其具有分隔等于或小于源极/漏极地址线的宽度的距离的通道插塞端侧壁，并且使得没有残留的掺杂半导体材料粘附到侧壁。类似地，本征半导体材料层被成形为使得没有残留掺杂的半导体材料粘附到通道插塞下面的本征半导体材料层的侧壁终止。

6. 发明授权

US5156986A Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration 失效
标题翻译：通过顶帽栅极电极配置对自对准TFTS中的源极/漏极 - 栅极重叠进行正向控制
公开(公告)号：US5156986A
公开(公告)日：1992-10-20
申请号：US667149
申请日：1991-03-11
申请人： Ching-Yeu Wei , George E. Possin , Robert F. Kwasnick
发明人： Ching-Yeu Wei , George E. Possin , Robert F. Kwasnick
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66765 , H01L21/28008 , H01L29/42384 , H01L29/4908
摘要： Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.
摘要翻译：通过包括具有不同蚀刻特性的两个不同导体的栅极导体层来提供薄膜晶体管中的栅极电极和源极和漏极之间的重叠长度的正向控制。作为栅极导体图案定义过程的一部分，蚀刻两个栅极导体以暴露下面的材料，并且根据栅电极和源之间的期望重叠，蚀刻回去上栅极导体层以暴露第一栅极导体层，以及漏电极。此后，使用平面化和非选择性蚀刻方法，用相对于第二栅极导体层自对准的源极和漏极制造器件的其余部分。

7. 发明授权

US4933296A N.sup.+ amorphous silicon thin film transistors for matrix addressed liquid crystal displays 失效
标题翻译：用于矩阵寻址液晶显示器的N +非晶硅薄膜晶体管
公开(公告)号：US4933296A
公开(公告)日：1990-06-12
申请号：US761938
申请日：1985-08-02
申请人： Harold G. Parks , William W. Piper , George E. Possin , Donald E. Castleberry
发明人： Harold G. Parks , William W. Piper , George E. Possin , Donald E. Castleberry
IPC分类号： H01L29/78 , G02F1/133 , G02F1/136 , G02F1/1368 , G09F9/35 , H01L21/285 , H01L21/336 , H01L21/77 , H01L21/84 , H01L27/12 , H01L29/45 , H01L29/786
CPC分类号： H01L29/66765 , G02F1/1368 , H01L21/28512 , H01L27/124 , H01L29/458 , G02F2202/103
摘要： A thin film FET switching element, particularly useful in liquid crystal displays (LCDs) employs particular materials and is fabricated via a particular process to ensure chemical compatibility and the formation of good electrical contact to an amorphous silicon layer while also producing FETs with desirable electrical properties for LCDs. These materials include the use of titanium as a gate electrode material and the use of N.sup.+ amorphous silicon as a material to enhance electrical contact between molybdenum source and drain pads and an underlying layer of amorphous silicon. The process of the present invention provides enhanced fabrication yield and device performance.
摘要翻译：特别适用于液晶显示器（LCD）的薄膜FET开关元件采用特定材料，并通过特定工艺制造，以确保化学相容性和与非晶硅层形成良好的电接触，同时还产生具有所需电性能的FET 用于LCD。这些材料包括使用钛作为栅极电极材料，以及使用N +非晶硅作为材料来增强钼源和漏极焊盘之间的电接触以及下一层非晶硅。本发明的方法提供了增强的制造产量和装置性能。

8. 发明授权

US4855806A Thin film transistor with aluminum contacts and nonaluminum metallization 失效
标题翻译：具有铝触点和非铝金属化的薄膜晶体管
公开(公告)号：US4855806A
公开(公告)日：1989-08-08
申请号：US241271
申请日：1988-09-07
申请人： Harold G. Parks , William W. Piper , George E. Possin , Donald E. Castleberry
发明人： Harold G. Parks , William W. Piper , George E. Possin , Donald E. Castleberry
IPC分类号： G02F1/1368 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/77 , H01L21/84 , H01L29/49 , H01L29/786
CPC分类号： H01L21/28008 , G02F1/1368 , H01L21/28512 , H01L27/124 , H01L29/4908 , H01L29/66765 , H01L29/78618 , H01L29/78669 , G02F2202/103
摘要： A thin film FET switching element, particularly useful in liquid crystal displays, employs a set of special materials to ensure compatibility with the indium tin oxide of a pixel electrode layer used as transparent conductive material in liquid crystal display devices. These materials include the use of titanium as a gate electrode material and the use of aluminum as a material to enhance electrical contact between source and drain pads and an underlying layer of amorphous silicon. The apparatus and process of the present invention provide enhanced fabrication yield and device reliability.
摘要翻译：特别适用于液晶显示器的薄膜FET开关元件采用一组特殊材料，以确保与用作液晶显示装置中的透明导电材料的像素电极层的氧化铟锡的相容性。这些材料包括使用钛作为栅极电极材料，以及使用铝作为材料来增强源极和漏极焊盘之间的电接触以及下层的非晶硅。本发明的装置和方法提供了增强的制造产量和装置的可靠性。

9. 发明授权

US4646424A Deposition and hardening of titanium gate electrode material for use in inverted thin film field effect transistors 失效
标题翻译：用于反向薄膜场效应晶体管的钛栅极材料的沉积和硬化
公开(公告)号：US4646424A
公开(公告)日：1987-03-03
申请号：US761937
申请日：1985-08-02
申请人： Harold G. Parks , George E. Possin
发明人： Harold G. Parks , George E. Possin
IPC分类号： C23C14/08 , C23C14/06 , C23C14/14 , G02F1/133 , G02F1/136 , G02F1/1368 , H01L21/336 , H01L27/12 , H01L29/49 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66765 , G02F1/1368 , H01L29/4908 , Y10S148/131
摘要： The gate electrode in an inverted field effect transistor (FET) is fabricated with titanium to provide an FET which is particularly suitable for use as the switching element in a matrix addressed liquid crystal display. More particularly, the resist employed in gate electrode patterning is plasma ashed in an oxygen atmosphere to toughen the titanium gate material and render it more amenable to subsequent processing steps.
摘要翻译：反向场效应晶体管（FET）中的栅电极由钛制成，以提供特别适合用作矩阵寻址液晶显示器中的开关元件的FET。更具体地，用于栅极电极图案化的抗蚀剂是在氧气氛中等离子体灰化以增韧钛栅极材料并使其更适于随后的处理步骤。

10. 发明授权

US4212082A Method for fabrication of improved storage target and target produced thereby 失效
标题翻译：制造改进的存储目标和由此产生的目标的方法
公开(公告)号：US4212082A
公开(公告)日：1980-07-08
申请号：US898620
申请日：1978-04-21
申请人： William D. Barber , George E. Possin
发明人： William D. Barber , George E. Possin
IPC分类号： G11C11/23 , G11C13/02 , C25D11/32
CPC分类号： G11C11/23
摘要： An improved target for storage of electric charge, in an electron beam addressable memory, utilizes an anodic oxide grown upon a semiconductor layer, forming part of a semiconductor diode structure. The anodic oxide is overlayed with a planar film of conductive material and the target structure is scanned with an electron beam for writing of electric charge storage therein and reading of the electron charge patterns therefrom over relatively greater numbers of erase/write operations relative to a target having a thermally-grown oxide layer.
摘要翻译：在电子束可寻址存储器中，用于存储电荷的改进目标利用在半导体层上生长的阳极氧化物，形成半导体二极管结构的一部分。阳极氧化物覆盖有导电材料的平面膜，并且目标结构用用于写入电荷的电子束扫描，并且通过相对于目标的相对较多数量的擦除/写入操作读取电子电荷模式具有热生长的氧化物层。

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