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1. 发明授权

US5156986A Positive control of the source/drain-gate overlap in self-aligned TFTS via a top hat gate electrode configuration 失效
标题翻译：通过顶帽栅极电极配置对自对准TFTS中的源极/漏极 - 栅极重叠进行正向控制
公开(公告)号：US5156986A
公开(公告)日：1992-10-20
申请号：US667149
申请日：1991-03-11
申请人： Ching-Yeu Wei , George E. Possin , Robert F. Kwasnick
发明人： Ching-Yeu Wei , George E. Possin , Robert F. Kwasnick
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49
CPC分类号： H01L29/66765 , H01L21/28008 , H01L29/42384 , H01L29/4908
摘要： Positive control over the length of the overlap between the gate electrode and the source and drain electrodes in a thin film transistor is provided by a gate conductor layer comprising two different conductors having differing etching characteristics. As part of the gate conductor pattern definition process, both gate conductors are etched to expose the underlying material and the upper gate conductor layer is etched back to expose the first gate conductor layer in accordance with the desired overlap between the gate electrode and the source and drain electrodes. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the second gate conductor layer using a planarization and non-selective etch method.
摘要翻译：通过包括具有不同蚀刻特性的两个不同导体的栅极导体层来提供薄膜晶体管中的栅极电极和源极和漏极之间的重叠长度的正向控制。作为栅极导体图案定义过程的一部分，蚀刻两个栅极导体以暴露下面的材料，并且根据栅电极和源之间的期望重叠，蚀刻回去上栅极导体层以暴露第一栅极导体层，以及漏电极。此后，使用平面化和非选择性蚀刻方法，用相对于第二栅极导体层自对准的源极和漏极制造器件的其余部分。

2. 发明授权

US5340758A Device self-alignment by propagation of a reference structure's topography 失效
标题翻译：通过参考结构的地形的传播进行设备自对准
公开(公告)号：US5340758A
公开(公告)日：1994-08-23
申请号：US938562
申请日：1992-08-28
申请人： Ching-Yeu Wei , George E. Possin , Robert F. Kwasnick
发明人： Ching-Yeu Wei , George E. Possin , Robert F. Kwasnick
IPC分类号： H01L29/40 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66765 , H01L21/28008 , H01L29/42384 , H01L29/78669
摘要： A self-aligned, inverted, thin film field effect transistor is produced by patterning the gate electrode to have tapered edges followed by conformal deposition of subsequent layers of the device structure up through a support layer followed by deposition of a subordinate layer such as the source/drain metallization) on the support layer. The subordinate layer itself may be a planarization or non-conformal layer or may have a subsequent non-conformal planarization layer disposed thereon. Thereafter, the structure is non-selectively etched (preferably reactive ion etched) until the support layer is exposed by the creation of an aperture in the subordinate layer in alignment with raised portions of the reference layer while leaving the subordinate layer present on other parts of the structure. Thereafter, the remainder of the device is fabricated with the source and drain electrodes self-aligned with respect to the gate conductor using a selective etch method.
摘要翻译：通过对栅电极进行图案化以产生渐缩边缘，随后将器件结构的后续层向上保持沉积通过支撑层，随后沉积下层（例如源极）而产生自对准反转的薄膜场效应晶体管 /漏极金属化）。下层本身可以是平面化或非保形层，或者可以具有设置在其上的随后的非保形平面化层。此后，结构被非选择性蚀刻（优选为反应离子蚀刻），直到支撑层通过在下位层中形成与参考层的凸起部分对准的孔而暴露，同时使下层存在于其它部分结构。此后，使用选择性蚀刻方法，使源极和漏极相对于栅极导体自对准制造器件的其余部分。

3. 发明授权

US5293417A X-ray collimator 失效
标题翻译： X射线准直仪
公开(公告)号：US5293417A
公开(公告)日：1994-03-08
申请号：US30909
申请日：1993-03-15
申请人： Ching-Yeu Wei , Robert F. Kwasnick , George E. Possin
发明人： Ching-Yeu Wei , Robert F. Kwasnick , George E. Possin
IPC分类号： G21K1/02
CPC分类号： G21K1/025
摘要： A collimator for use in an imaging system with a radiation point source is formed from a plurality of collimator plates stacked together. Passages in each collimator plate in conjunction with the respective passages in adjoining plates form a plurality of channels through the collimator. The channel longitudinal axes are aligned with selected orientation angles that correspond to the direct beam path from the radiation source to the radiation detectors. The collimator plates are made up of patterned sheets of radiation absorbent material or alternatively comprise patterned photosensitive material substrates coated with a radiation absorbent material. The cross-sectional shape of each channel corresponds to the cross-sectional shape of the radiation detecting area of the detector element adjoining the channel. A method of forming a collimator includes the steps of selectively removing material from the collimator plates to form the passages therein, and stacking the patterned collimator plates together to align them so that the respective adjacent passages form a channel aligned with respective selected orientation angles corresponding to direct paths of radiation from the radiation source to the detector elements in the assembled array.
摘要翻译：用于具有辐射点源的成像系统中的准直器由堆叠在一起的多个准直器板形成。每个准直板中的通道与相邻板中的相应通道结合形成通过准直器的多个通道。通道纵向轴线对应于对应于从辐射源到辐射探测器的直接光束路径的选定取向角度。准直板由图案化的辐射吸收材料片构成，或者包括涂覆有辐射吸收材料的图案化感光材料基底。每个通道的横截面形状对应于邻近通道的检测器元件的辐射检测区域的横截面形状。一种形成准直器的方法包括以下步骤：选择性地从准直板移除材料以在其中形成通道，并且将图案化的准直器板堆叠在一起以对准它们，使得相应的相邻通道形成与各自选定的取向角对应的通道从辐射源到组装阵列中的检测器元件的直接辐射路径。

4. 发明授权

US5231655A X-ray collimator 失效
标题翻译： X射线准直仪
公开(公告)号：US5231655A
公开(公告)日：1993-07-27
申请号：US802789
申请日：1991-12-06
申请人： Ching-Yeu Wei , Robert F. Kwasnick , George E. Possin
发明人： Ching-Yeu Wei , Robert F. Kwasnick , George E. Possin
IPC分类号： G21K1/02
CPC分类号： G21K1/025
摘要： A collimator for use in an imaging system with a radiation point source is formed from a plurality of collimator plates stacked together. Passages in each collimator plate in conjunction with the respective passages in adjoining plates form a plurality of channels through the collimator. The channel longitudinal axes are aligned with selected orientation angles that correspond to the direct beam path from the radiation source to the radiation detectors. The collimator plates are made up of patterned sheets of radiation absorbent material or alternatively comprise patterned photosensitive material substrates coated with a radiation absorbent material. The cross-sectional shape of each channel corresponds to the cross-sectional shape of the radiation detecting area of the detector element adjoining the channel. A method of forming a collimator includes the steps of selectively removing material from the collimator plates to form the passages therein, and stacking the patterned collimator plates together to align them so that the respective adjacent passages form a channel aligned with respective selected orientation angles corresponding to direct paths of radiation from the radiation source to the detector elements in the assembled array.
摘要翻译：用于具有辐射点源的成像系统中的准直器由堆叠在一起的多个准直器板形成。每个准直板中的通道与相邻板中的相应通道结合形成通过准直器的多个通道。通道纵向轴线对应于对应于从辐射源到辐射探测器的直接光束路径的选定取向角度。准直板由图案化的辐射吸收材料片构成，或者包括涂覆有辐射吸收材料的图案化感光材料基底。每个通道的横截面形状对应于邻近通道的检测器元件的辐射检测区域的横截面形状。一种形成准直器的方法包括以下步骤：选择性地从准直板移除材料以在其中形成通道，并且将图案化的准直器板堆叠在一起以对准它们，使得相应的相邻通道形成与各自选定的取向角对应的通道从辐射源到组装阵列中的检测器元件的直接辐射路径。

5. 发明授权

US5241192A Fabrication method for a self-aligned thin film transistor having reduced end leakage and device formed thereby 失效
标题翻译：具有减小的端部泄漏的自对准薄膜晶体管的制造方法以及由此形成的器件
公开(公告)号：US5241192A
公开(公告)日：1993-08-31
申请号：US862125
申请日：1992-04-02
申请人： George E. Possin , Ching-Yeu Wei
发明人： George E. Possin , Ching-Yeu Wei
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/786
CPC分类号： H01L29/78696 , H01L27/1214 , H01L29/66765 , Y10S438/978
摘要： The TFT structure formed in accordance with this invention includes a TFT body that has channel plug end sidewalls separated by a distance equal to or less than the width of the source/drain address lines and such that no residual doped semiconductor material adheres to the sidewalls. Similarly, the intrinsic semiconductor material layer is shaped such that no residual doped semiconductor material adheres to the sidewalls of the intrinsic semiconductor material layer underlying the channel plug ends.
摘要翻译：根据本发明形成的TFT结构包括TFT体，其具有分隔等于或小于源极/漏极地址线的宽度的距离的通道插塞端侧壁，并且使得没有残留的掺杂半导体材料粘附到侧壁。类似地，本征半导体材料层被成形为使得没有残留掺杂的半导体材料粘附到通道插塞下面的本征半导体材料层的侧壁终止。

6. 发明授权

US5324674A Fabrication method for a self-aligned thin film transistor having reduced end leakage and device formed thereby 失效
标题翻译：具有减小的端部泄漏的自对准薄膜晶体管的制造方法以及由此形成的器件
公开(公告)号：US5324674A
公开(公告)日：1994-06-28
申请号：US43999
申请日：1993-04-05
申请人： George E. Possin , Ching-Yeu Wei
发明人： George E. Possin , Ching-Yeu Wei
IPC分类号： H01L21/336 , H01L21/77 , H01L21/84 , H01L29/786 , H01L21/265
CPC分类号： H01L29/78696 , H01L27/1214 , H01L29/66765 , Y10S438/978
摘要： A thin film transistor (TFT) having reduced end leakage is fabricated by: forming a gate electrode on a substrate; forming a TFT body disposed over the gate electrode, the TFT body comprising an intrinsic semiconductor material layer, a channel plug disposed on the intrinsic semiconductor material layer over the gate electrode, a doped semiconductor material layer on the intrinsic semiconductor material and the sidewalls of the channel plug, and a source/drain metallization layer; selectively etching the source/drain metallization layer to form an address connection line and a pixel connection line to a respective source electrode tip and drain electrode tip, selectively etching the channel plug to remove the portion of the sidewalls not adjoining the source and electrode tips that had been in contact with the doped semiconductor layer; removing the doped semiconductor layer portion not underlying the address connection line, the pixel connection line, and the source and drain electrode tips; and removing the now-exposed portion of the intrinsic semiconductor layer material that had been in contact with the doped semiconductor material.
摘要翻译：通过在基板上形成栅电极来制造具有减少的端漏的薄膜晶体管（TFT）形成设置在所述栅电极上的TFT体，所述TFT体包括本征半导体材料层，设置在所述栅电极上的所述本征半导体材料层上的沟道插塞，所述本征半导体材料上的掺杂半导体材料层和所述本体半导体材料的侧壁沟道插塞和源极/漏极金属化层; 选择性地蚀刻源极/漏极金属化层以形成地址连接线和到相应的源极电极尖端和漏极电极尖端的像素连接线，选择性地蚀刻沟道插塞以去除不邻接源极和电极尖端的侧壁部分，已经与掺杂半导体层接触; 去除不在地址连接线下方的掺杂半导体层部分，像素连接线以及源极和漏极电极尖端; 以及去除已经与掺杂半导体材料接触的本征半导体层材料的现在曝光部分。

7. 发明授权

US5430298A CT array with improved photosensor linearity and reduced crosstalk 失效
标题翻译： CT阵列具有改进的光电传感器线性度和减少的串扰
公开(公告)号：US5430298A
公开(公告)日：1995-07-04
申请号：US264098
申请日：1994-06-21
申请人： George E. Possin , Ching-Yeu Wei
发明人： George E. Possin , Ching-Yeu Wei
IPC分类号： G01T1/20 , G01T1/24 , G06T1/00 , H01L27/14 , H01L27/146
CPC分类号： G01T1/2018 , H01L27/14676
摘要： A computed tomography (CT) imager includes a scintillator and a photosensor array optically coupled to the scintillator through an optical coupling layer. The photosensor array includes a plurality of photosensitive devices disposed in a block so as to receive incident light from the scintillator through a first surface of the block; each photosensitive device forms a pixel in the array, and each pixel further has a fully photoactive region in which the quantum efficiency of the photosensor is greater than about 65%. The optical coupling layer further includes a pixel boundary light barrier that is made of light absorptive material disposed in the optical coupling layer overlying the areas on the photosensor array first surface between respective fully photoactive regions of the photosensitive devices. The pixel boundary light barrier is disposed to absorb substantially all light photons passing along a path between the scintillator and pixels in the photosensor array other than the pixel underlying the portion of the scintillator in which the light photons were generated, thereby reducing noise and cross-talk in the array and enhancing the linear operating characteristics of photosensors in the array.
摘要翻译：计算机断层摄影（CT）成像器包括闪烁体和通过光耦合层光耦合到闪烁体的光电传感器阵列。光传感器阵列包括设置在块中的多个感光装置，以便通过块的第一表面接收来自闪烁器的入射光; 每个光敏器件在阵列中形成像素，并且每个像素还具有完全光活性的区域，其中光电传感器的量子效率大于约65％。光学耦合层还包括像素边界光栅，其由设置在光耦合层中的光吸收材料制成，该光耦合层覆盖感光器件的各个完全光活性区域之间的光传感器阵列第一表面上的区域。像素边界光栅被设置为吸收沿着闪烁体和光电传感器阵列中的像素之间的路径的基本上所有的光子，除了其中产生光子的闪烁体部分之下的像素之外，由此减少噪声和交叉，在阵列中讲话并增强阵列中光电传感器的线性运行特性。

8. 发明授权

US5198694A Thin film transistor structure with improved source/drain contacts 失效
标题翻译：具有改善的源极/漏极触点的薄膜晶体管结构
公开(公告)号：US5198694A
公开(公告)日：1993-03-30
申请号：US825218
申请日：1992-01-24
申请人： Robert F. Kwasnick , George E. Possin , David E. Holden , Richard J. Saia
发明人： Robert F. Kwasnick , George E. Possin , David E. Holden , Richard J. Saia
IPC分类号： H01L21/3213 , H01L21/336 , H01L29/45
CPC分类号： H01L29/66765 , H01L21/32139 , H01L29/458 , Y10S438/97
摘要： Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.
摘要翻译：通过采用具有第一相对薄的第一导体层和第二相对较厚的第二导体层的源极/漏极金属化，薄膜晶体管中的最小线间距减小，并且线间隔均匀性增加。第二导体被选择为可以在第一导体存在的情况下优先蚀刻的导体，由此第一导体充当用于图案化源极/漏极金属化的第二导体部分的蚀刻剂的蚀刻停止。该蚀刻优选使用干蚀刻进行。干蚀刻通常比湿式蚀刻提供对线宽度的更好的控制。第二导体的蚀刻可以通过干法蚀刻工艺进行，该蚀刻工艺以基本上与第二导体相同的速率蚀刻光致抗蚀剂，由此第二导体设置有大致为45°的侧壁斜率，这提高了后续提供的钝化质量共形钝化层的沉积。

9. 发明授权

US5273920A Method of fabricating a thin film transistor using hydrogen plasma treatment of the gate dielectric/semiconductor layer interface 失效
标题翻译：利用栅极电介质/半导体层界面的氢等离子体处理制造薄膜晶体管的方法
公开(公告)号：US5273920A
公开(公告)日：1993-12-28
申请号：US939746
申请日：1992-09-02
申请人： Robert F. Kwasnick , George E. Possin
发明人： Robert F. Kwasnick , George E. Possin
IPC分类号： H01L21/30 , H01L29/786 , H01L21/265
CPC分类号： H01L29/4908 , H01L21/3003 , H01L29/66765 , H01L29/78669 , Y10S438/91
摘要： A method of fabricating a thin film transistor (TFT) includes the steps of forming a gate conductor on a substrate; depositing a gate dielectric layer of silicon nitride over the gate conductor; treating the exposed silicon nitride on the surface of the gate dielectric layer with a hydrogen plasma at a power level of at least 44 mW/cm.sup.2 for at least 5 minutes; depositing a layer of amorphous silicon semiconductor material over the gate dielectric layer; depositing a layer of n+ doped silicon over the treated amorphous silicon surface; depositing a layer of source/drain metallization over the n+ doped layer; and patterning the source/drain metallization and portions of the underlying n+ doped layer to form source and drain electrodes. The deposition of the TFT material layers and the hydrogen plasma treatment is preferably by plasma enhanced chemical vapor deposition.
摘要翻译：制造薄膜晶体管（TFT）的方法包括在基板上形成栅极导体的步骤; 在栅极导体上沉积氮化硅栅极电介质层; 用至少44mW / cm 2的功率水平的氢等离子体处理所述栅极电介质层的表面上暴露的氮化硅至少5分钟; 在所述栅极电介质层上沉积非晶硅半导体材料层; 在所处理的非晶硅表面上沉积n +掺杂硅层; 在n +掺杂层上沉积一层源极/漏极金属化层; 以及图案化源极/漏极金属化层和下层n +掺杂层的部分以形成源极和漏极。 TFT材料层的沉积和氢等离子体处理优选通过等离子体增强化学气相沉积。

10. 发明授权

US5527726A Self-aligned thin-film transistor constructed using lift-off technique 失效
标题翻译：使用剥离技术构建的自对准薄膜晶体管
公开(公告)号：US5527726A
公开(公告)日：1996-06-18
申请号：US425269
申请日：1995-04-17
申请人： George E. Possin , Robert F. Kwasnick
发明人： George E. Possin , Robert F. Kwasnick
IPC分类号： H01L29/78 , H01L21/027 , H01L21/336 , H01L29/786 , H01L21/265
CPC分类号： H01L29/66765 , H01L21/0274 , Y10S148/10 , Y10S148/102 , Y10S148/105
摘要： A thin-film field-effect transistor is fabricated by forming an electrically insulative island between the source and the drain. A cap is formed on the island with a brim that overhangs the island. A layer of source-drain metal, which will subsequently constitute the source and drain contacts, is then deposited upon the source, the drain, and the cap, but the overhang creates an exposed region which can be attacked by an etchant. When the etchant is applied, it etches away the cap, thereby lifting off the source-drain metal which coated the cap, leaving the fully formed source and drain contacts separated by the island.
摘要翻译：通过在源极和漏极之间形成电绝缘岛来制造薄膜场效应晶体管。在岛上形成一个帽子，一个悬垂在岛上的边缘。随后将构成源极和漏极触点的源极 - 漏极金属层沉积在源极，漏极和帽上，但是突出部产生可被腐蚀剂侵蚀的暴露区域。当施加蚀刻剂时，其蚀刻掉盖，从而提起涂覆盖的源极 - 漏极金属，留下由岛隔开的完全形成的源极和漏极接触。

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